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The key role that underfill materials play in highly reliable, advanced flip chip organic packages has generated an increased focus on their behavior and structure. One such behavior relates to the observation of filler separation from the resin matrix which, to date, has been predominantly attributed to gravity or capillary flow. The phenomenon of silica filler separation is discussed in the context...
There are increasing interest in high temperature endurable sensor or device packaging solution for a set of wide ranging applications that include oil and gas production or deep sea exploration, advanced automotive application, aerospace, more electric aircraft initiative (MEA) or engine health management (EHM) systems, geothermal energy harvesting as well as other renewable energy industries. Besides...
Fan-Out (FO) chip on substrate is one of the fan-out solution for package integration. This solution brings the short interconnection between die to die for excellent electrical performance. Fan-Out chip on substrate device provides excellent electrical performance in multi-die connection,. The multiple re-distribution layer (RDL) processing is implemented in advance multi-dies FO chip on substrate...
We have investigated finite element method (FEM) modeling of thermal stress analysis in a SiC power module using sintering Ag die-attach, and explored the reliability focusing on the initial cracking point caused by the thermal stress. The analysis results by FEM models support our experimental observations in the reliability tests of the fabricated modules, confirming that using direct-bonded-copper...
For the high-power LED applications, TAV (Through-aluminum-nitride-via) substrate with a high thermal conductivity provides better heat dissipation. However, the high thermal expansion coefficient mismatch between the AlN (Aluminum nitride) and copper film may cause the failure, and thus affect the reliability of TAV substrate. The objective of this study is to evaluate the reliability of TAV substrate...
Fan-out chip on substrate (FOCoS) is defined as the fan-out package flip-chip mounts on high pin counts ball grid array substrate. 12-inch advanced wafer level package (aWLP) process is implemented on FOCoS for cost saving advantage. The fan-out package constructs from multi-chips with short interconnection between die to die (D2D) by re-distribution layer (RDL) process, which has the potential for...
Molded underfill (MUF) process for system in package with WLCSP package with cu pillar bump would be the future application in SIP module assembly due to small form factor and low cost of WLCSP and good electrical, thermal performance, fine pitch and lower cost of cu pillar bump. However, higher stiffness of cu pillar could cause interface fracture between cu pillar and solder bump during SMT process...
Mechanical stress induced by mechanical and thermal loading on thin silicon devices breaks the devices at a certain load called the fracture or breaking strength of the device. The displacement experienced by the dies, due to bending, at fracture strength is called the fracture displacement. The strength properties of thin, bare silicon dies have already been reported. This work extends the study...
DC/DC converters are widely used in industrial, aerospace and other fields. The reliability of DC/DC converters is very important for the whole electronic system. Overheat is the key factor infecting the reliability of DC/DC converters because of the power density of the device. Three-dimensional thermal analysis modules include heat distribution analysis and thermal stress analysis at 25 °C in this...
The trends towards miniaturization in the electronics industry coupled with advances in flip chip technology have increased the use of flip chip on board or direct chip attach technology in many products. This is especially true for products where re-work is not an option. Reliability issues were overcome by the use of underfill to couple the chip to the substrate and subsequently significant advances...
Semiconductor industry has recognized the need to replace traditional Al/SiO2 interconnects with Cu/Low-k interconnects in the mainstream electronics devices following the latter's impact on power, RC delay, and cross-talk reduction. However due to lower elastic modulus, strength, and poor adhesion characteristic, reliability of the Cu/Low-k interconnects turns out to be a concern for its integration...
Flip chip technology has attracted much attention in electronic industry as it fills the need for low cost, miniaturization and high performance requirements of electronic products. For such devices, package reliability under drop impact is a great concern to the manufacturers as these electronic packages are very much vulnerable to solder joint failures caused by the mechanical shock and the PCB...
With increasing data traffic requirements to support mobile devices, tablets and computers, the need for faster internet traffic is mushrooming. The routers and switches used to drive network traffic need to deliver high bandwidth and speed. Key to achieving this high speed and bandwidth is ensuring closer integration between the Application Specific Processors (ASICs) and Memory devices. Consequently,...
TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. he stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method...
Through-silicon-via (TSV) technology permits devices to be placed and wired in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to many advantages of TSV application. However, there are also some challenges for stacked die package with TSVs. One of the challenges is thermo-mechanical reliability of multi-layer...
In order to meet the demands for the high-density, high-performance, high-speed, smaller form factor and multi-function integration in portable electronic products, novel packaging technology now trends toward system in package (SiP) technology. 3D packaging technology is one of the most optimum means to achieve SiP. The embedded technology is one of the 3D packaging solutions and playing a key role...
The fabrication of embedded passives represents a promising solution for system in package (SiP) regarding the reduction of size and assembly costs. But the thermo-mechanical deformation caused by residual stress generated from embedded passives processing have a significant impact on reliability of embedded passives. Due to the complication of embedded passives processing, there are several challenges...
In electronic product, reliability of solder joint has big impact on the function of the whole electronic product. In the design period of the package, it is important to predict solder joint thermal fatigue lifetime and analyze the effect of each factors on the lifetime of solder joint. Finite Element Analysis (FEA) based solder joint lifetime prediction method, which used Anand viscoplastic constitutive...
Glass has long been used for photovoltaic (PV) module covers and thin-film (TF) module substrates and superstrates. These applications typically use float glass of soda-lime-silica composition and thickness ≥ 3.2 mm. Thin specialty glass is being considered as a replacement for substrates and superstrates for dual-glass laminated TF PV modules. This study focuses on module in-service stresses and...
This paper describes chip solder joint reliability on three substrate types: one board SMI (aluminium substrate) and two different boards in FR4. Several chip sizes and types (resistor, capacitor) were assembled on these boards. Accelerated Thermal cycles (ATC) -55/+125??C were applied to evaluate the lifetime of chip solder joints. The different results obtained showed an important dispersion in...
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