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Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and creation of embedded multiprocessors architecture system focusing on its design area and performance. Embedded...
Understanding the structure and function of DNA sequences represents an important area of research in modern biology. Unfortunately, analysis of such data is often complicated by the presence of mutations introduced by evolutionary processes. At the lowest scale, these usually occur in biological sequences as character substitutions, insertions or deletions (indel). They increase the time-complexity...
With increasing demand for different data rates and services for communication systems, reconfigurability is of utmost importance. Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the configuration bit stream. Low complexity turbo-like codes based on simple two-state trellis or simple graph structure results in decoder with low complexity...
This paper presents an 8-bit FPGA implementation of a discrete time cellular neural network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split&Shift techniques to have a 31 times 31 grid that processes more than 2500 images per second. As this work evolves from a previous binary DTCNN implementation, results are compared...
A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
A new high precision serial multiplier with most significant digit first (MSDF) is presented. This one uses a borrow-save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2's complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as...
Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases...
We present an FPGA-based co-processor for accelerating computations associated with Singular Value Array Reconciliation Tomography (SART), a recently developed method for RF source localization. The co-processor allows this relatively complex computational task to be performed using less hardware and less power than would be required by a microprocessor-based computing cluster with comparable throughput...
Fourth-order cross moments are used in modern digital signal processing as a powerful analytical tool for the synthesis and analysis of signals and systems. Computing fourth-order cross moments from incoming time-series data is computationally intensive process and requires fast computing systems and parallel processing techniques to meet the real time processing requirement. An algorithm based on...
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