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The LEON series of processors has enabled space missions during the two past decades. This paper discusses the past, present and future of the LEON series of SPARC 32-bit space-grade microprocessors and system-on-chip devices.
In this work, we present a modular software subsystem that exposes a set of APIs for supporting the automation of a set of design choices in the synthesis of a hardware accelerator by a proprietary FPGA toolchain. We model the subsystem around Vivado, Xilinx's proprietary FPGA toolchain, in order to provide a finer grained control on the toolchain's features with respect to the standard .tcl interface...
A central processing unit (CPU) and peripheral devices are discussed for which all data processing and data transfer is uniquely time tagged using a timestamp generated by the embedded processing system master clock. The Time Aware Processor (TAP) introduces time into the processor computing language to relate data to temporal events, including the processors own internal functions.
FPGA devices allows designer to implement complex digital architectures that involve hardware and software components. Because of the different features of hardware and software design, diverse mechanisms and tools have been proposed for debugging and verification of architectures implemented on FPGA devices. Bus level transactions and data processing algorithms are usually difficult to manage together...
Software-Defined Networking (SDN) is a paradigm adopted in computer networks that decouple the control logic from the physical to the software layer, reducing the routers' complexity and enabling a high-level network awareness. This work explores the SDN paradigm on NoCs to manage Circuit Switching (CS) connections in an original Multi-Physical Network (MPN) architecture. Related works focus its CS...
The template matching is an important technique used in pattern recognition. It aims at finding a given pattern within a frame sequence. Pearson's Correlation Coefficient (PCC) is widely used to evaluate the similarity of two images. This coefficient is computed for each image pixel, which entails a computationally very expensive process. This paper proposes an implementation of the template matching...
Clock tree of a complex system-on-chip is modeled across different design stages independently, resulting in multiplication of time and effort needed to develop clock tree models. Model-based design is an emerging methodology that can improve the efficiency, time, and cost of a system design. We propose an approach to modeling clock tree of a complex system-on-chip by exploiting patterns in hardware...
This paper describes the architecture and design of a Bluetooth Low Energy Controller. The designed controller consists of a hardware and software part.
Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact product time-to-market. This paper introduces a new approach to evaluate, at early design phase, the reliability of a computing system running a software. The approach can be used when the hardware architecture is not completely defined...
By means of a management framework and programmable routing tables, Software Defined Network (SDN) architectures offer network's adaptability to today's computer systems. In Networks-on-Chip (NoC) based systems, management methods have been implemented as specific solutions unable to be reused in further designs. A Software Defined NoC (SDNoC) architecture will permit on-the-fly re/configuration and...
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from...
Vital computers play a fundamental role in the safety-critical industrial applications. It is necessary to conduct functional safety analysis against its application (logic) software to guarantee the functionality of the whole system to reach the domain-requested safety integrity level. However, the diversity of application software brings difficulty to the conduction of safety analysis with a high...
The cyclic redundancy check (CRC) is a popular error detection code (EDC) used in many digital transmission and storage protocols. Most existing digit-serial hardware CRC computation architectures are based on one of the two well-known bit-serial CRC linear feedback shift register (LFSR) architectures. In this paper, we present and investigate a generalized CRC formulation that incorporates negative...
This work proposes a reconfigurable system able to perform - through a parallel and pipelined core, called ReCPU - regular expression matching. The system can configure on the programmable device, such as a FPGA, a set of ReCPUs, each one exploiting a single instance of the regular expression matching task on the given input string. These cores work in parallel on the same string analyzing different...
The performance of memory system depends majorly on types of instruction constructs, speedup of executions, capacity of processing elements and scheduling techniques. Most scheduling techniques are faced with several challenges such as multiple issues, exploiting more parallelism in programs instructions, speedup rate of executions and support for conditional instructions constructs. Recent innovations...
Prototyping distributed embedded system can be seen as a collection of many requirements covering many domains. System designers and developers need to describe both functional and non-functional requirements. Building distributed systems is a very tedious task since the application has to be verifiable and analyzable. Architecture Analysis and Design Language (AADL) provides adequate syntax and semantics...
KySat-2 is a 1U CubeSat launched on the NASA ELaNa IV mission on November 19, 2013. The Command & Data Handling (C&DH) architecture for KySat-2 leverages aspects of the Space Plug-and Play Avionics (SPA) standard developed by the Air Force Research Laboratory (AFRL) and adapts it to the constraints of the CubeSat form factor. The design eases interfacing commercial-off-the-shelf (COTS) and...
The Fast Inverse Square Root algorithm has been used in 3D games of past for lighting and reflection calculations, because it offers up to four times performance gains. This paper presents a hardware implementation of the algorithm on an FPGA board by designing the complete architecture and successfully mapping it on Xilinx Spartan 3E after thorough functional verification. The results show that this...
Generation of device-unique digital signatures using Physically Unclonable Functions (PUFs) is an active area of research for the last decade. However, most PUFs are conceived and designed as stand-alone hardware modules. In contrast, this paper proposes a PUF architecture that is tightly integrated into the core of a system-on-chip (SoC), with the purpose of creating a physical SoC authentication...
The paper presents an optimized architecture of cascaded integrator-comb (CIC) digital filter structure. The structure is suitable for implementation in application specific integration circuits (ASICs) or field programmable gate arrays (FPGAs). The main advantages of the architecture are higher working frequency, smaller area size and lower power consumption. Software in C++ language was written...
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