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As a popular deep learning technique, convolutional neural network has been widely used in many tasks such as image classification and object recognition. Convolutional neural network exploits spatial correlations in the images by performing convolution operations in local receptive fields. Convolutional neural networks are preferred over fully connected neural networks because they have fewer weights...
This paper presents an artificial neural network (ANN) model based design for Hénon chaotic systems, and its equivalent hardware model for hardware co-simulation using Field Programmable Gate Arrays (FPGA). Chaotic generators can be used for the study of chaotic behaviors of brain activities captured by Electroencephalogram (EEG). The ANN model is designed with different fixed-point data format and...
Scaling CMOS integrated circuit technology leads to decrease the chip price and increase processing performance in complex applications with re-configurability. Thus, VLSI architecture is a promising candidate in implementing neural network models nowadays. Backpropagation algorithm is used for training multilayer perceptron with high degree of parallel processing. Parallel computing implementation...
This paper presents FPGA-based ECG arrhythmia detection using an Artificial Neural Network (ANN). The objective is to implement a neural network based machine learning algorithm on FPGA to detect anomalies in ECG signals, with a better performance and accuracy, compared to statistical methods. An implementation with Principal Component Analysis (PCA) for feature reduction and a multi-layer perceptron...
Spike generation and routing is typically the most energy-demanding operation in neuromorphic hardware built using spiking neurons. Spiking neural networks running on neuromorphic hardware, however, often use rate-coding where the neurons spike rate is treated as the information-carrying quantity. Rate-coding is a highly inefficient coding scheme with minimal information content in each spike, which...
For decades, feedforward neural network (FNN) based classifiers have been extensively used in many classification problems such as image and speech recognition. The inherent parallel nature of the FNN classifier makes it a good candidate for hardware implementations in order to obtain a performance speed up, since most of its computations are matrix-vector multiplications, where the input images arranged...
This paper presents an implementation of Perceptron algorithm using DataFlow approach. DataFlow is a new paradigm that is suitable for solving BigData problems in applications. The iterative nature of the algorithm and a large training set make it suitable for implementing on DataFlow accelerators. Also we discuss differences between ControlFlow paradigm, which is based on the von Neumann architecture,...
In this paper the implementation of a virtual sensor is presented, using an artificial neural network (ANN) in an FPGA system, which will serve to estimate the speed of a DC motor. The acquisition and processing of signals RNA training and detailed architecture implemented in the FPGA is shown. Finally the behavior of the virtual sensor is analyzed in normal and abnormal operating conditions.
Artificial Neural Networks (ANNs) find applications in engineering solutions to complex problems. The usefulness of ANNs in real-time embedded applications can be enhanced if feasible architectures for their hardware implementation can be customized to provide an attractive tradeoff between area and performance. In this paper, we present a real-time embedded hardware implementation of a feed-forward...
Neural networks have been of interest for long, but have been hard to implement in practice, because of excessive complexity and training required. Neural networks have been proposed with hardware, such as with FPGAs and VLSI. This paper proposes implementing neurons and neural networks with MOS Flash memory technology. The floating gate of the flash memory can store a charge for years, influencing...
This paper describes the design of an auto-associative memory based on a spiking neural network (SNN). The architecture is able to effectively utilize the massive interconnect resources available in FPGA architectures as a good match to the axons in biological neural networks. A complete implementation of the memory on a single FPGA is presented. The signal processing circuitry is composed from simple,...
In this paper, we propose an architecture for FPGA-implementation of neural adaptive neural network RF power behavioral modeling. The real-valued time-delay neural network (RVTDNN) and the backpropagation (BP) learning algorithm were implemented on FPGA using Xilinx System Generator for DSP and the Virtex-6 FPGA ML605 Evaluation Kit. Performances obtained with 16-QAM modulated test signal and material...
Hardware implementation of Neural Networks (NNs) provides advantages such as parallelism and real-time capabilities, whereas Probabilistic Neural Networks (PNNs) achieve high accuracy in pattern discrimination. In this paper, a FPGA implementation of a PNN sorting algorithm is proposed to sort spikes. Both Matlab-based and FPGA-based sorting algorithms using a PNN were implemented and evaluated, and...
Probabilistic Neural Network has been considered as providing superior performance for neural decoding. However, the huge computation burden costs high resource in FPGA, which limits its scalability. In this paper, an improved FPGA implementation of Probabilistic Neural Network for neural decoding is developed and evaluated on the Xilinx Virtex-5 platform. The proposed implementation reduces the resource...
Dedicated hardware implementations of artificial neural networks promise to provide faster, lower power operation when compared to software implementations executing on processors. Unfortunately, custom hardware implementations do not support intrinsic training of these networks on-chip. Training is typically done using software simulations and the obtained network is synthesized and targeted to hardware...
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