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Multiplier is one of the major hardware circuits of microprocessor and high performance systems such as digital signal processor; FIR filters, processing operations like Convolution, Cross Correlation, and auto-correlation of discrete signals, digital Image processing applications such as edge detection etc. The major design constraint of multiplier is speed which is affected due to propagation delay...
FinFET transistor has much better short-channel characteristics than traditional planar CMOS transistor and will be widely used in next generation technology. Due to its significant structural difference from conventional planar devices, it is essential to revisit whether existing fault models are applicable to detect faults in FinFET logic gates. In this paper, we study some unique defects in FinFET...
This paper presents a novel automated post-layout flow validation tool to intensively test the MOSFETs and passive components in 32nm, 28nm and 22nm Process Design Kits (PDK). Benchmark circuits, such as, ring oscillator, logic circuits and passive delay circuits, are automatically generated, LVS (layout versus schematic) checked, extracted and simulated in multiple Model/LVS/Parasitic extraction(PEX)...
In this paper the graph energy and electrical power consumption of various parallel prefix adders (PPA) are measured and investigated. By comparison the graph energy of PPAs with their power consumption, a linear relation between them is considered. Moreover, the measurements represent direct relation between arcs number and graph energy in PPA structures. Using these results a new PPA (proposed I)...
This paper presents a novel logi-thermal simulator architecture. A logi-thermal simulator encorporates a logic and a thermal core in strong coupling. It is capable of calculating the self-heating of digital blocks and is able to account for the consequences of temperature change by implementing the delays of the blocks as a function of the temperature. The simulator architecture presented is able...
A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area...
A 4-bit Asynchronous multiplier was designed in the sub-threshold regime. The multiplier, using asynchronous completion detection, is more tolerant to process variation than conventional synchronous sub-threshold circuits and operates with a supply voltage as low as 150mV. The average energy per computation was simulated at 1.13pJ. The minimum energy voltage was simulated at 350mV, with an average...
Advanced semiconductor technologies use mechanical stress to enhance carrier mobility and achieve higher performance. Layout dependence of induced stress causes the stress profile, and hence the carrier mobility along the device channel, to vary across device width. Additionally, sub-wavelength lithography causes printed shapes to deviate from drawn rectilinear shapes, resulting in non rectangular...
In this paper, we propose two new N-way arbiter circuits. One circuit is based on the token-ring arbiters and another circuit is based on the mesh arbiters. The idea of the ring arbiter is to generate a lock signal by a token which is based on the non-return-to-zero signaling. It can achieve low latency and high throughput arbitration for a heavy work load environment. The idea of the mesh arbiter...
In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters...
As the minimum feature size shrinks down far below sub-wavelength, Restricted Design Rule(RDR) or layout regularity plays an important role for maintaining pattern fidelity in photo lithography. However, it also incurs overheads in layout area and circuit performances. Therefore it is important to find an appropriate level of regularity that gives the best trade-or among manufacturability, cost, and...
IR-drop problem during test mode exacerbates delay defects and results in false failures. In this paper, we take the X-filling approach to reduce IR-drop effect during at-speed test. The main difference between our approach and the previous X-filling methods lies in two aspects. The first one is that we take the spatial information into consideration in our approach. The second one is how X-filling...
This paper presents a method that considers thermal effects in logic simulations. The aim is to develop a tool that is capable of modeling the thermal behavior of a digital circuit and, at the same time, yields results almost at the speed of ordinary logic simulators. The importance of such a simulation is that thermal effects can be the cause of signal integrity problems. The structure and the basic...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper studies the impact of intra-die random variability on low-power digital circuit designs, specifically, circuit timing failures due to intra-die variability. We identify a new low-Vdd statistical failure mode that is strongly supply-voltage dependent and also introduce a simple yet novel method for quantifying the effects of process variability on digital timing - a delay overlapping stage...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
As mainstream processing technology advances into 65 nm and beyond, many factors that were previously considered secondary or insignificant, can now have an impact on chip timing. One of these factor is inversed temperature dependence (ITD). As supply voltage continues scaling into sub-IV territory, delay-temperature relationship can be reversed on some cells, meaning that device switching time may...
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