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The host-multi-SIMD chip multiprocessor (CMP) architecture has been proved to be an efficient architecture for high performance signal processing which explores both task level parallelism by multi-core processing and data level parallelism by SIMD processors. Different from the cache-based memory subsystem in most general purpose processors, this architecture uses on-chip scratchpad memory (SPM)...
With the advance of semiconductor, multi-core architecture is inevitable in today's embedded system design. Nested loops are usually the most critical part in multimedia and high performance DSP (Digital Signal Processing) systems. Hence, maximizing loop parallelism is an important issue to improve the performance of a modern compiler. This paper studies how to maximize the system performance with...
The multimedia framework is designed to provide easy to use services for developing multimedia applications based on an embedded platform. With the rapid advances in multimedia technology, various types of codec have been developed. Most of them achieve good performance but construct with complicated algorithms. Moreover, the current computing load of embedded system is still carried by MPU, and its...
The computation speed offered by nowadays embedded systems allows combining advanced signal processing and data acquisition in dedicated architectures optimized for given applications. Such architectures can be used for 2D/3D signal analysis and reconstruction in such broad areas as: medical signal processing - tomography object reconstruction (USG, PET, CT, OCT, etc.), biomedical image analysis -...
This paper proposes a novel algorithm and hardware architecture for an embedded stereo vision system which is appropriate for robotics applications. In this paper we distributed this process to three re-programmable processor unit as pre-processing, post-processing and stereo matching. In order to accomplish with on two Digital Signal Processors (DSPs) for the pre and post processing as well as a...
Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead loop...
For next-generation audio applications, the dominant trends are much higher sample rate, larger word length and more audio channels for playback audio data. Traditional DSPs or embedded processors are inefficient for such kinds of applications because of their non-specific or limited computing capabilities as well as the on-chip memory architectures. In this paper, an embedded audio processor aiming...
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance VLIW processor core in an FPGA. Architecture based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance...
This paper presents an open-architecture embedded manufacturing control (EMC) system based on Windows CE.net, which is a multi-task embedded real-time operating system (RTOS). The EMC system adopts a master-slave architecture, And the Master applies with Windows CE.net, which charges weak real-time tasks, while the slave adopts a motion control card based on Digital Signal Processor (DSP) and Field...
In order to solve an intra-system interface for chip-to-chip and board-to-board communications and meet the explosive demand for higher bandwidth and more efficient signal processing and data transmission in typical embedded system, here is an active demand that adopting a new system interconnect technology to ensure that bus performance continues to increase. The RapidIO is proposed in the paper...
This article describes a kind of embedded solution for Digital Television Network Tester adopting ARM-DSP dual processor system architecture. This architecture considers flexible control of ARM processor and strong signal-processing capability of DSP processor, combines decoding technology of digital television transmission channel and embedded technology. The advantage of abundant software and nice-looking...
Sensor processing is a common task within many embedded system domains, such as in control systems, the sensor feedback is used for actuator control. In this paper we have surveyed several embedded system domains, and extracted kernels of computation that are common across applications within a given domain, or across domains. We have shown that adding architectural support for executing these common...
This paper summarizes the experiences of global faculty (N. America, Europe, Asia) in using an open design platform approach for project-based active learning in electronics, computing and ICT engineering education. A common design platform was used to support courses spanning a range of university engineering levels from 2nd year undergraduate to 2nd second year postgraduate programs, and across...
Ubiquitous and pervasive computing systems are characterized by intelligent sensing and computing. These systems seamlessly understand and respond to the environment with little human intervention. Since such systems are required to be small and inobtrusive, embedded systems play an important role in their design. Furthermore, these systems need to run sophisticated applications in a resource constrained...
This paper describes the architecture and hardware generation concept of a parameterized MAC unit for use in a scalable embedded DSP core. The MAC unit supports a broad set of instructions for integer and fractional datatypes. Its generation is controlled by architectural as well as implementation and placement parameters. Including structured physical placement in the generation process ensures fast...
In this paper, we present a new fully programmable heterogeneous multi-core processor architecture for SDR (software defined radio). To meet the computation properties of different algorithms, our solution contains three types of processor cores: two SIMD (Single Instruction Multiple Data) cores, four general purpose DSP cores and an embedded controller core. In order to verify the efficiency of our...
Digital signal processors (DSPs) are very efficient devices to implement algorithms for signal processing and analyzing. Endowing sensorial nodes from a sensor network with such processing cores it could lead to high performance because of the possibility of parallel and distribute processing and thus reducing the quantity of information spread into the network (network load). If such a node uses...
Transport triggered architecture (TTA) is one kind of application-specific instruction processors (ASIP), which fits embedded systems and offers a cost-effective trade-off between the energy-efficiency and performance. However its architecture and very long instruction word (VLIW) are alike, which also results in a very poor code density. In embedded systems, memory is one of the most expensive resources...
AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform independent software package is developed for AVS1-P2 decoder to facilitate embedded video codec development. In order to minimize the on-chip memory and save the time consumed in on-chip/off-chip data...
Advances in chip technology have enabled integrating many functional units on a single chip. This led to the emergence of the concept of system-on-chip (SoC) which is used extensively in the development of advanced embedded systems. Embedded systems are widely used today in different digital signal processing (DSP) applications that usually require high computation power and tight constraints. Using...
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