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There are many available NAT64 implementations, but we can not measure their performance per the standards, due to the lack of complaint testers. The aim of our effort is to design and write the first implementation of a test program that could provide the first answer to these needs. For benchmarking Network Interconnect Devices we could use the recommendation of the 2544 (IP version independent)...
While the horizontal integrated circuit design process is extensively practiced, untrusted foundries can impose significant threats on the security of final products. A carefully inserted extra circuitry as a hardware trojan in a circuit layout can interfere with circuit functionality under very rare circumstances with inconsiderable footprints. In this paper, we introduce a novel layout-level vulnerability...
To minimize the access latency of set-associative caches, the data in all ways are read out in parallel with the tag lookup. However, this is energy inefficient, as only the data from the matching way is used and the others are discarded. This paper proposes an early tag lookup (ETL) technique for L1 instruction caches that determines the matching way one cycle earlier than the cache access, so that...
Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that the compiler tool chain must handle the increased complexity. However, it is not clear if current production...
In the low power design of integrated circuits, multiple power modes and clock gating are the two common techniques to reduce dynamic power consumption. In the multiple power modes designs, replacing some of the normal buffers with adjustable delay buffers (ADBs) and assign different delay values in different power modes is one of the promising solutions to satisfy the clock skew constraint, and clock...
Bias Temperature Instability (BTI)-induced transistor aging degrades path delay over time and may eventually induce circuit failure due to timing violations. Chip health monitoring is therefore necessary to track delay changes on a per-chip basis. We propose a method to accurately predict the fine-grained circuit-delay degradation with minimal area and performance overhead. It re-uses on-chip design-for-test...
As transistor feature size scales down, soft errors in combinational logic because of high-energy particle radiation is gaining increasing concerns. In this paper, a soft error mitigation method based on accurate mathematical modeling of SER and addition of non-invert functionally redundant wires (FRWs) is proposed. In the proposed method, the factors which have significant influences on SER because...
Software-based path delay fault testing (SPDFT) has been used to identify faulty chips that cannot meet timing constraints due to gross delay defects. In this paper, we propose using SPDFT for a new purpose - aggressively selecting the operating point of a variation-affected design. In order to use SPDFT for this purpose, test routines must provide high coverage of potentially-critical paths and must...
Hardware designers tend to focus more on function correctness and performance parameters of the system than information security. As a result, hardware devices are disclosing confidential information through system side effects, which is vulnerable to attackers. Unfortunately, conventional security countermeasures such as encryption algorithms and access control mechanisms are inefficient in preventing...
Hardware Trojan detection is a very important topic especially as parts of critical systems which are designed and/or manufactured by untrusted third parties. Most of the current research concentrates on detecting Trojans at the testing phase by comparing the suspected circuit to a golden (trusted) one. However, these attempts do not work in the case of third party IPs, which are black boxes with...
Multicores may satisfy the growing performance requirements of critical Real-Time systems which has made industry to consider them for future real-time systems. In a multicore, the bus contention-control policy plays a key role in system's performance and the tightness of the Worst-Case Execution Time (WCET) estimates.
Power consumption is a critical aspect in today's mobile environment, while high-throughput remains a major design goal. To satisfy both low-power and high-throughput requirements, parallelism has been employed. In this paper we present an approach to reducing power dissipation in the design of sum-of-products operation by utilizing parallel hardware while maintaining high-throughput. The proposed...
With technology scaling, integrated circuits (ICs) suffer from increasing process, voltage, and temperature (PVT) variations and adverse aging effects. In most cases, these reliability threats manifest themselves as timing errors on critical speed-paths of the circuit, if a large design guard band is not reserved. This work presents a novel insitu timing error masking technique, namely InTimeFix,...
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