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Implementation of digital modulators on Field Programmable Gate Array (FPGA) is a research area that has received great attention recently. Most of the research has focused on the implementation of simple digital modulators on FPGAs such as Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK), and Phase Shift Keying (PSK). This paper presented a novel method of implementing Quadrature Phase...
This paper describes part of project that implemented the image processing of a CMOS sensor for endoscopic purposes. The sensor is a small sized device of 1×1mm2 and the image processing has been done inside a FPGA. This part of the work describes the implementation of the Gamma function with a balance between the resources needed and the accuracy. A linear piecewise solution was used that stores...
The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
In this work the numerical considerations to arise when making a control system on FPGA are presented. It takes as study case the implementation of the position controller of a manipulator robot. The system is made using two numerical representations: integer and fixed-point. It shows the procedure to define the width in bits of the integer and fractional part of the fixed-point number. In addition,...
Spatial image filters are one of the primary operators in digital image processing and edge detection is one of their most well-known operations. Because of growing demand in applications such as real time video processing and stream image processing, accelerating this family of algorithms based on FPGA platforms has received increased attention. This paper introduces a new implementation of this...
Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel...
In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices — amount of FPGA resources used and maximum delay,...
The regularity of resources found in FPGAs is a unique feature, which can be utilized in a number of applications, e.g., in timing critical applications or applications with a demand for homogeneous routing. Current synthesis tools do not support an automatic generation of homogeneous FPGA designs, such that a time-consuming hand-crafted design is required. We present a tool flow, which automatically...
This paper demonstrates an economical implementation of Gaussian Minimum shift keying (GMSK) modulator for Global System for Mobile communication (GSM) system using the basics of direct waveform synthesis. This method makes use of pre-calculated filter response of Gaussian filter for pulse shaping and Phase concatenation circuit for accumulation. Baseband in-phase and quadrature-phase component generation...
This paper presents the development and implementation of a generalized backpropagation multilayer perceptron (MLP) architecture described in VLSI hardware description language (VHDL). The development of hardware platforms has been complicated by the high hardware cost and quantity of the arithmetic operations required in online artificial neural networks (ANNs), i.e., general purpose ANNs with learning...
Proportional Integral Derivative (PID) controller is the most preferable controller in industries that does not require precise analytical model of the system to be controlled. This paper presents a design and implementation of PID (Proportional-Integral-Derivative) controller based on FPGA (Field-Programmable Gate Arrays) for low voltage synchronous buck Converter. Matlab/Simulink environment is...
This paper describes a design strategy that makes viable hardware implementations of Information-Set (IS)-based decoders with near-MLD performance. This is achieved through three main developments: i) a criterion that reduces the number of candidate codewords, without significant performance loss; ii) a modified, hardware-friendlier version of the Dorsch algorithm; and iii) detailed circuit analysis...
In order to increase the flexibility of control for stepper motor, a pulse generator based on FPGA is proposed in this paper. Draw State transition diagram by analysis the Principle of pulse generator, and realized in FPGA using Very High-speed Integrated Circuit Hardware Description Language (VHDL). The simulate results show that pulse output in FPGA is consistent with the requirements. The module...
In a satellite, there exist various communication subsystem like Telecommand, Telemetry and Payload data transfer. Depending on the requirements of a particular system, different modulation techniques are being used. In general, M-PSK modulation techniques are preferable as they are power and bandwidth efficient. The paper presents the digital implementation QPSK & 8-PSK modulators for satellite...
Finite impulse response(FIR) Band-pass filter is widely used in many digital signal processing. Its advantage is good linear phase character for designing any amplitude frequency characteristic, which is very critical to real-time digital signal processing. In this paper, we analyzed the filter's structure and traditional algorithms, and pointed out the weakness, and then proposed an optimal distributed...
In this paper a new Context-Adaptive Variable Length Coding (CAVLC) encoder architecture is proposed aimed to be implemented in embedded systems and field programmable logic. The design proposes novel Arithmetic Table Elimination (ATE) techniques, along with a table compression technique applied to those tables that cannot be eliminated by arithmetic manipulations. These approaches allows to halve...
Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process,...
With increasing demand for different data rates and services for communication systems, reconfigurability is of utmost importance. Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the configuration bit stream. Low complexity turbo-like codes based on simple two-state trellis or simple graph structure results in decoder with low complexity...
The existing direct digital frequency synthesis (DDFS) only can generate one kind of waveform with one read-only memory lookup table (ROM LUT), which cannot provide inphase wave and quadrature wave for global position system(GPS) carrier tracking. A DDFS is designed based on ROM LUT. Using the symmetry of the sine wave and the property that cosine waveform is leading or lagging one fourth period compared...
Since the end of 2008, the first FPGAs based on asynchronous logic cells are commercially available. Although the internal logic of the FPGA fabric is based on pure asynchronous logic, the design style for asynchronous FPGAs does not differ from that of classical FPGAs. The design for asynchronous FPGAs can be synthesized in the same way as for synchronous FPAGs from register transfer level based...
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