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In this paper, we propose an energy-efficient approximate multiplier design approach. Fundamental to this approach is configurable lossy logic compression, coupled with low-cost error mitigation. The logic compression is aimed at reducing the number of product rows using progressive bit significance, and thereby decreasing the number of reduction stages in Wallace-tree accumulation. This accounts...
A new asynchronous early output section-carry based carry lookahead adder (SCBCLA) with alias carry output logic is presented in this paper. To evaluate the proposed SCBCLA with alias carry logic and to make a comparison with other CLAs, a 32-bit addition operation is considered. Compared to the weak-indication SCBCLA with alias logic, the proposed early output SCBCLA with alias logic reports a 13%...
Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for...
Susceptibility of modern ICs to radiation-induced faults constitutes a matter of great concern in the recent years. Particularly, the transient faults and their impact on the combinational logic remain an intriguing issue, since the evaluation of their behavior is quite significant, especially for critical systems, for the development of error-resistant techniques in design process. For an accurate...
A random access analog memory is designed without static power in this work. The analog memory appears the benefit on the great reduction of interconnections but suffers from the static power consumption and inaccuracy. As a hybrid, the hexadecimal signal processing is targeted in this paper. For storing hexadecimal values even implementing hexadecimal sequential logic, a master-slave structure is...
A new true-single-phase-clock (TSPC) divide-by-2/3 prescaler is presented in this work. By merging one of the branches of the TSPC D flip-flops (DFF) and the modified dual-modulus control circuit, we can realize a divide-by-2/3 prescaler with only 5-stage TSPC logic gates and fewer transistors compared with the conventional designs. Analysis shows that the load capacitance at output of the proposed...
Today as technology has reached up to 7nm, meeting timing constraints at such technology node has become very difficult. The experimentations have been done over a multi-clock processor block on 32 nm node where several algorithms for optimization techniques are used. The used algorithms include optimization features such as buffer sizing, gate sizing, delay insertion, buffer and gate relocation and...
Negative Bias Temperature Instability (NBTI) is a prominent physical failure mechanism which severely degrades the performance of PMOS transistors whenever the voltage at the gate is negatively biased. It leads to catastrophic timing violations in critical circuits and a severe shortening of the overall operational lifetime of the entire system. To alleviate such damaging effects due to NBTI, we present...
In order to obtain high channel boosting potential and to reduce a program disturbance in channel stacked type with layer selection by multi-level operation (LSM), a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. To verify the validity of the new method in LSM, TCAD simulations are...
A compact nanoscale device emulating the functionality of biological synapses is an essential element for neuromorphic systems. Here we present for the first time a synapse based on a single ferroelectric FET (FeFET) integrated in a 28nm HKMG technology, having hafnium oxide as the ferroelectric and a resistive element in series. The gradual and non-volatile ferroelectric switching is exploited to...
The capability of bi-directional, underwater power transfer (both sending and receiving power) increases the functionality of underwater vehicles by allowing them to be charged and provide charge wirelessly to other systems without leaving the water. To minimize the footprint of the charging circuitry, a single transistor-based full-bridge circuit can be used to either send or receive power. This...
This paper describes a cloud-based digital design environment for ASIC and FPGA. We call it CloudV. CloudV is built using open-source as well as homegrown EDA software tools. The ultimate goal of CloudV is to reduce the design costs by relying on cloud infrastructure and on collaborative design. Currently, CloudV v 1.0 allows students to gain hands-on experience in digital ASIC design tasks covering...
Many algorithms for gate size and threshold voltage (VT) optimization have been proposed. The International Symposium of Physical Design (ISPD) contests for discrete gate sizing with wire loads have led to improved algorithms. However, significant changes in cell sizes require re-placement and re-routing which invalidate the wire loads upon which the sizing was performed. In turn, sizing must be re-performed...
Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security properties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to...
Among the various memories, Ternary Content Addressable memory (TCAM) is used to give a high speed of searching operation. In ordinary memories, like static random access memories (SRAM), the address is given and data is given as output, but in TCAM the data is given as input and address is given as output. However it is having some disadvantages like less bit density, slow access time, more searching...
Asynchronous quasi-delay-insensitive (QDI) circuits are a promising solution for coping with aggressive process variations faced by modern technologies, as they can gracefully accommodate gate and wire delay variations. The literature proposes several QDI design templates with different trade-offs, giving designers a large spectrum of options to use, adapt or even mix. Among these, NULL Convention...
Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactance of global clock networks at a given resonance frequency, fo, have been proposed. Conventionally, such schemes are only suitable at high multi-GHz frequencies in order to be able...
As the transistor process technology continues to scale, the aging effect posits new challenges to the already complex static timing analysis (STA) process. In this paper, we first observe that aging can be thought of a type of correlated dynamic on-chip variations (OCV), and identify the problem introduced by such type of OCV. In particular, we take the negative bias temperature instability (NBTI)...
Increasingly more software-based applications are being developed and deployed in modern vehicles. As a result, the extensibility of a system design has become an important issue in order to accommodate more future applications and update of existing ones on one hand and reduce the effort and cost of re-design, test and validation on the other. In this paper, we discuss the extensibility-driven design...
A large number of emerging applications such as implantables, wearables, printed electronics, and IoT have ultra-low area and power constraints. These applications rely on ultra-low-power general purpose microcontrollers and microprocessors, making them the most abundant type of processor produced and used today. While general purpose processors have several advantages, such as amortized development...
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