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Open source hardware projects are becoming more and more common. OpenRISC SOC, one of the prominent of these projects, has become quite popular with the support of volunteer developers. In this work, we have demonstrated the design of an DES (Data Encryption Standard) based system, that can be used in security applications, on ORPSoC-v2 (Openrisc Reference Platform System-on-Chip). Additionally, we...
As the complexity of System-on-Chip (SoC) and the reuse of third party IP continues to grow, the security of a heterogeneous SoC has become a critical issue. In order to increase the software security of such SoC, the TrustZone technology has been proposed by ARM to enforce software security. Nevertheless, many SoC embed non-trusted third party Intellectual Property (IP) trying to take the benefits...
The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present...
As VLSI technology growing exponentially, silicon chips can accommodates more cores on chip this will lead to very high computational power but poor communication among on-chip processors and memory. To overcome this we proposed spatial division multiplexing based network-on-chip with modified network interface. Proposed network interface provide high throughput with optimized area and consume very...
From the point of view of system development, this paper introduces a FPGA based parallel AD acquisition board and its implementation process. The board uses 24-bit 8 channels of TI to synchronize the sampling chip ADS1278 to synchronize the input signals of the 8 input signals. FPGA uses Altera's EP2AGX45F572, Nios II processor running on it as the core of data processing. Communication between CY7C68013...
In VLSI system design speed, area, and power are the three parameters playing a vital role. Among them the speed is purely determined by the delay taken by the design for its processing. In the delay, the design delay is mainly decided by gate delay. Nowadays in the design, the path or routing delay dominates more towards the design delay compare to the earlier days where gate delay dominates more...
To qualify a System-on-Chip (SoC) for automotive standards, all the interfaces have to be thoroughly checked against the specifications/standards. Sensor protocols which are new to the automotive world don't have the complete range of sensors available as of today for checking the complete features. These sensors operate over a limited range, are not capable of generating all possible frame formats,...
Hardware Trojans compromise security by invalidating the assumption that hardware provides a root-of-trust for secure systems. We propose a novel approach for an FPGA system-on-chip (SoC) to ensure confidentiality of trusted software despite hardware Trojan attacks. Our approach employs defensive techniques that feature morphing on-chip resources for moving target defense against fabrication-time...
A modern system-on-a-chip includes tens to hundreds of modules such as processor cores, memories and other IP blocks and exchanges packetized data using highperformance interconnection networks as a subsystem for data transport. This paper reports the implementation of an industry-wide network on a chip in FPGA, and the first implementation and evaluation of the Sonics Performance Monitor and Hardware...
The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform...
A SoC design of H.264 Video Encoding system is implemented based on FPGA in this paper. Intra prediction algorithm and baseline profile is selected, and H.264 encoder algorithm is designed as an IP core and embedded to the SoC through the interconnect interface AMBA AXI bus. The SoC is implemented on Xilinx Zynq-7000 FPGA and each functional module is simulated by Modelsim and tested within the SoC...
With the development of the cloud computing, the servers we use today are not suitable for data centers very well because of high power consumption and low density. In this paper, we propose a cloud server of low power consumption, high density and good scalability. We employ a reconfigurable architecture to build the cloud server and we can change or update the architecture of the cloud server from...
One of the most important problems for mission critical space-borne computing systems employing FPGA devices is fault tolerance to transient and permanent hardware faults. In many cases, the ability for run-time self-recovery from such faults is a vital feature. This paper presents a method and mechanism for run-time recovery of FPGA-based System-on-Chip (SoC) based on Collaborative Macro-Function...
With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the...
For most multi-modal stream processing tasks Dynamic Reconfigurable Systems-on-Chip (SoC) have demonstrated high efficiency in cost and power. These systems utilize partial reconfiguration for dynamic adaptation to changes in the workload or in environment. Mostly, reconfiguration mechanisms are based on central resource management sub-systems deployed in a CPU-core. In this paper we propose a novel...
Advancements in silicon, software and IP support have made Field Programmable Gate Arrays (FPGAs) a highly flexible solution for many applications. With the growing number of companies providing IP support for FPGAs, IP license violations by over-deployment of IP into more devices than originally licensed remains a major concern for IP owners. In this paper we present a solution for secure IP exchange...
ARM-based servers are garnering increasing interest in big data processing for their low power consumption. However, they are ill-suited for compute-intensive tasks due to their poor processing capability compared to the CPUs used in a traditional server. This paper describes our early efforts to integrate the processing power of the FPGA with the ARM processor inside the Xilinx Zynq SoC. An eight-slave...
We propose a unified methodology for optimizing IPv4 and IPv6 lookup engines based on the balanced range tree (BRTree) architecture on FPGA. A general BRTree-based IP lookup solution features one or more linear pipelines with a large and complex design space. To allow fast exploration of the design space, we develop a concise set of performance models to characterize the tradeoffs among throughput,...
Recently introduced chips with ARM based processors and programmable logic provide huge potential for digital signal processing, networking and other applications. Many IP cores and operating systems have been prepared for these chips to simplify the development process. Nevertheless, the integration of IP cores and operating system is not covered by any development tool yet. Developers have to design,...
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