The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, the principle of normalized minimum-sum (NMS) polar decoding process is explored. It is demonstrated that with one properly chosen parameters for NMS algorithm, performances approach to that of the sum-product (SP) algorithm can be achieved. As well, the complexity reduction is realized by calculating a linear function instead of nonlinear function. Simulation results for successive...
This paper focuses on low complexity architectures for check node processing in Non-Binary LDPC decoders. To be specific, we focus on Extended Min-Sum decoders and consider the state-of-the-art Forward-Backward and Syndrome-Based approaches. We recall the presorting technique that allows for significant complexity reduction at the Elementary Check Node level. The Extended-Forward architecture is then...
Low-density parity-check (LDPC) coded massive multiple-input and multiple-output (MIMO) scheme is getting increasingly popular and sophisticated in today's wireless communication systems, since it can highly improve the spectral efficiency, data rates, and error performance. In this paper, a novel iterative detection and decoding (IDD) method for LDPC-coded massive MIMO systems is proposed. Based...
Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on...
In this paper, iterative decoding using Belief Propagation λ-min decoding algorithm is considered. In this algorithm check nodes use only the λ lowest-magnitude messages thus simplifying the hardware complexity and reducing memory usage. A parallel-input architecture is proposed for the check node. We focus on the determination of the sought minima in a parallel fashion. Novel simplified circuits...
LDPC still receives extensive attention in the field of channel coding because of its superior error correction performance, high throughput and low decoding complexity. Considering the poor adaptability and limited expansibility of traditional LDPC decoder, a design method of LLR-BP decoder based on adaptive code length is proposed. A partial parallel LDPC decoder structure is designed under the...
Low-density parity-check convolutional codes (LDPC-CC) have interesting error correction features. They have a great potential to become a key error-correcting codes for enhancing reliability of modern digital communication systems, optical systems and storage devices. On the implementation side, however, the design of low-cost low-power and high-throughput LDPC-CC decoders remains challenging. This...
Polar code has become a major milestone in information theory field in recent times. Researchers are still observing more efficient encoding and decoding structures. In this study, a new WIB based structure is proposed which reduces the computational complexity of WIB introduced as an early termination method for BP polar decoder in literature. Both proposed and WIB methods are implemented with VHDL...
Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as...
This paper proposes an area efficient and low power Reed-Solomon (RS) decoder. The proposed decoder is designed using eight stage arithmetic pipelined architecture. The pipelined architecture of RS decoder performs the detection of error locator from the input stream and computes the error magnitude polynomial using the Berleykamp Massey's algorithm. The evaluation of error locator and computation...
LDPC convolutional codes (LDPC-CC) are a family of error-correcting codes (ECC) used in digital communication systems like the IEEE 1901 standard. High throughput and low complexity hardware architectures were designed for real time systems. In this article we demonstrate that an efficient selection of the message passing (MP) algorithm for LDPC-CC decoding improves the architecture features of related...
For polar codes, cyclic redundancy check (CRC)-aided successive cancellation list (CA-SCL) decoder has attracted increasing attention from both academia and industry. In this paper, a hardware efficient and low-latency CA-SCL polar decoder based on distributed sorting is first proposed. For path metric (PM) sorting of each level, a distributed sorting (DS) algorithm is proposed to reduce the comparison...
Fractional pixel interpolation for motion compensation is considered among the most computational consuming areas in High Efficiency Video Coding (HEVC). An efficient design and optimized hardware implementation for HEVC motion compensation are presented. This architecture is implemented for 8K HEVC decoder. A new scaling factor for interpolation filter and a modified number of Luma filter taps are...
In this paper, a hardware-efficient folded SC polar decoder based on k-segment decomposition is first proposed. The proposed k-segment scheme employs (k – 1) N1/k-bit decoders to implement the original N-bit decoder, and reduces the number of mixed-nodes from (N – 1) to (k ă 1)( N1/k – 1) with slightly increased latency. In addition, pipelining technique, partial parallel processing, and pre-computation...
Characterization of a Sparse Code Multiple Access (SCMA) decoder is performed to measure its error performance and its time and hardware implementation complexity. SCMA is a non-orthogonal technique proposed to support massive connectivity in future 5G wireless telecommunication systems. The reported SCMA decoder is based on the Message Passing Algorithm (MPA). The complexity of SCMA decoding is characterized...
This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, for LSC with list size l (l > 1), the l instances of successive cancellation (SC) decoder can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop...
Rise in bandwidth requirement for multimedia processing is forcing designers to use complex or wider buses in SOCs. Compression schemes using bit serial codes offer a low complexity encoding solution to such problems. However, their inherent sequential nature makes it challenging to achieve real time throughput at the decoder end. Conventionally, this problem is addressed by high frequency application...
Conventional bit-flipping (BF) algorithms spectacularly fail to handle punctured LDPC codes as they use hard decisions and, therefore, they cannot effectively cope with zero-reliability punctured symbols. However, BF techniques lead to low-cost high-speed decoders. This paper introduces a novel method that enables the use of BF-based iterative decoders for punctured LDPC codes. An erasure preprocessor...
Low Density Parity Check (LDPC) codes have been widely used in communications systems due to their high error correction capabilities. Recently these codes are also investigated for being exploited in high performance storage systems, especially when Non-Volatile Memory (NVM) technologies are used. The main drawback of using LDPC codes in storage systems with a high number of parallel channels is...
Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures are mandatory. State-of-the-art decoding algorithms result in architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.