The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With the scaling down of electronic devices and the boom of wireless communications, more and more smart devices are interconnected in what we call the Internet of Things. Connecting devices of everyday use can greatly improve our comfort, but it can also introduce unprecedented security problems. With billions of devices connected there is a huge risk of unauthorized use. In this context, Physical...
A new fully digital high resolution time-to-digital converter (TDC) based on a self-timed ring oscillator (STR) is presented. The proposed TDC can virtually achieve as fine as desired time resolution by simply increasing its number of stages thanks to the STR unique features. Moreover, the proposed technique allows on-the-fly time measurement on fast non-periodic signals. The TDC has been implemented...
In this paper, an area efficient time to digital converter (TDC) performing measurements between multiple hit signals is proposed. Our TDC is based on a delay line configured as a ring oscillator and a round tracker to count the number of iterations through the oscillator. Lookup tables configured as distributed RAMs and shift registers are used to sample the oscillator and the round tracker states...
The Physically Unclonable Functions (PUFs) are used in numerous security applications such as device authentication, secret key generation, FPGA intellectual property (IP) protection, and trusted computing. In this paper, compact implementations of Ring oscillator-based PUF (RO-PUF), Arbiter-based PUF (A-PUF) and RS Latch-based PUF (RS-LPUF) on an FPGA (Field Programmable Gate Array) platform are...
This paper proposes RTN-PUF, a novel PUF that utilizes random telegraph noise (RTN) of transistors as the physical uniqueness of individual devices. Our proposed RTN-PUF generates a response from a pair of ring oscillators (ROs) by comparing the numbers of frequency changes, which depend on the time constants of RTN. Due to the log-uniform distribution of the time constants, our RTN-PUF provides more...
In this work we present a complete end-to-end interface for a capacitive micromachined ultrasonic transducer (CMUT) intended for low-power gas sensing applications. A prototype chip was designed in a 0.18-μm BiCMOS process. Different blocks (a BJT-based Colpitts oscillator, an inverter-based oscillator, a sine-to-square wave converter, a digital frequency counter, and a parallel-to-serial converter)...
This thesis introduces the working principle of the universal counter frequency and period measurement and expounds the important function of the crystal oscillator inside universal counter. This paper designs a system which uses the technologies of time-sharing control and video capture to realize the automatic test of multiple crystal oscillators inside the universal counters at the same time.
Although Adaptive RED (ARED) algorithms, which can adjust RED's parameters adaptively are broadly researched to deal with dynamic network scenarios, including bursty traffic and varying link state, unstability is still a constraint against the improvement of efficiency. In this paper, TCP/RED system is considered as a feedback system where equilibrium exists. Through analyzing the proposed system,...
This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148fsrms...
An 8-bit, 3-stage asynchronous gated ring oscillator (GRO) time-to-digital converter (TDC) is presented. It employs asynchronous techniques to achieve minimum GRO stages. This lead to about 40% to 70% gate count reduction compared to synchronous GRO-TDC. Count-missing, glitch, and unnecessary addition are eliminated. The uncorrupted noise shaping characteristic is obtained. The chip is implemented...
This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon...
A universal protection controller for Li-ion battery charger is proposed in this paper. First, an in-depth analysis on Li-ion battery charger protection has been made, then a detailed system description was given, and finally test results were presented. This IC provides battery thermal protection, due time termination, bad cell detection, automatic recharge and state indication, which are usually...
As the supply voltage shrinks with technology scaling, the slightest drop in the voltage level has a significant impact on chip functionality. It is, therefore, important to accurately measure supply voltage noise to evaluate the actual IR drop on-chip and to feed the results to a power management unit, which can scale the voltage and perform on-chip compensation based on the IR drop. In this paper,...
An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static CMOS logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits,...
Random number generators are one of basic cryptographic primitives used in cryptographic protocols. Most of true random number generators in field programmable gate arrays (FPGAs) employ the timing jitter from ring oscillator clocks as a source of randomness. The paper analyses the jitter generated in ring oscillators and it uses a simple physical model of jitter sources to show that the random jitter...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
An 11-bit, 50-Msps time-to-digital converter (TDC) using a multipath gated ring oscillator (GRO) with 6 ps of delay per stage achieves low power (2.2 to 21 mW) and small area of 160times260 mum in 0.13 mum CMOS. The structure also achieves first order noise shaping of the GRO quantization and mismatch noise; the resulting TDC error integrates to <100 fs (rms) in a 1 MHz bandwidth to achieve dynamic...
We designed and built a novel all-optical re-timing, re-amplifying, and re-shaping (3R) regeneration system based on terahertz optical asymmetric demultiplexers (TOADs) developed in our laboratory. The system is capable of parallel processing multiple wavelengths, a feature which will significantly improve the scalability of current wavelength division multiplexing (WDM) networks. Performance against...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.