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In this paper, a memristor with structure of Cu/ PEDOT:PSS/ Ta was fabricated at room temperature. The conductance could be modulated incrementally by pulse sequences. The amplitude, width, frequency and quantity of the pulse sequence play important roles in conductance variation, which is similar to the weight of synapses. Several important synaptic learning behaviors such as short-term potentiation...
We report a novel resistive random-access memory (RRAM) device with a graphene oxide (GO) composite film embedded with TiO2 nano-particles as its resistive switching layer. The efficient physi-(or chem-) sorption of TiO2 endows the GO/TiO2 composites with superior bipolar resistive switching behaviors, including low switching voltage (about ±1V), tight distributions of HRS and LRS, long retention...
Bistable resistive switching of polycrystalline La0.67Sr0.33MnO3 (LSMO) thin films prepared by pulsed laser deposition (PLD) was investigated by applying voltage pulses with current compliance. Metallic LSMO films sandwiched by Ag and Pt electrodes show nonvolatile and reversible resistance switching behavior from a higher resistance state to a lower state with no data loss upon continuous readout...
Summary form only given. Scaling down to tens of nanometers or even below is appealing for device miniaturization, on one hand, and for exploring/exploiting novel phenomena arising from nanometer-size effects. Ferroelectric (FE) materials have been proposed for nonvolatile ferroelectric random access memories since two decades (J.F. Scott and C.A.P.D. Araujo, 1989) and lateral dimensions of ca. 100...
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
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