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In this paper, a novel Direct Digital Frequency Synthesizer (DDFS) based on using non-uniform segmentation in sine-weighted Digital-to-Analog Convertor (DAC) is proposed. To generating beyond Nyquist frequency signal, parallel DACs with Return-To-Zero (RTZ) technique are used. In conventional DDFSs for generating signal, a Phase to Sine Mapper (PSM) is used that often includes a look-up table memory...
A 57–64 GHz 4-bit switch type phase shifter with low group delay deviation and low loss flatness using 90nm low power CMOS technology is presented in this paper. The proposed switched delay networks are using transmission lines to avoid process variation of small-size capacitors. It is also measured with excellent insertion loss flatness of ±0.8dB for a specific phase shifting state, across 57–64...
A new approach for d irect digital frequency synthesizer (DDFS) with analogue sine conversion is presented. The proposed DDFS adopts the ROM-less architecture with linear DAC to achieve higher speed operation and lower power consumption. Fabricated by 0.18-μm CMOS process, the DDFS employs a 9-bits pipe line accumulator to provide an 8-bits amplitude resolution for the DAC circuit. At 1-GHz clock...
A 4.5-GHz 256~511 multi-modulus frequency divider for frequency synthesizers is demonstrated. The proposed frequency divider is based on phase switching technique and cascade of divide-by-2/3 cells, it prevents the presence of control logic gates in the highest frequency division block in order to achieve the highest operation frequency under low power consumption; the division ratio is ranged from...
This paper presents a fast switching frequency synthesizer for a Mode-1 MB-OFDM UWB system. The proposed architecture with a new frequency plan is designed to simplify the synthesizer implementation for optimizing the system power consumption and sideband rejection ratio. This frequency generator consists of a single phase-lock-loop (PLL), a 12-phase coupled ring oscillator, tri-mode divider-by-2...
This paper presents a low power glitch-free dual-modulus (15/16) prescaler based on the phase-switching for Ultra-Wide Band (UWB) transceiver. An inherently glitch-free phase-switching prescaler is realized by the adoption of a reverse switching sequence without any additional complicated circuit. A simplified model of the source coupled logic (SCL) structure is proposed to optimize the power of the...
A fully integrated double frequency differential LC voltage controlled oscillator (VCO), used in the frequency synthesizer of 2.4GHz IEEE802.15.4/ZigBee Wireless Sensor Network (WSN), is designed and implemented based on TSMC 0.18μm RF CMOS process with low power dissipation and wide tuning range. The core circuit adopts complementary differential negative resistance LC oscillator structure and is...
A frequency synthesizer capable of generating all the 14 sub-band carrier frequencies in 3.1~10.6 GHz band for multiband OFDM ultra-wideband (MB-OFDM UWB) transceivers is proposed. It is composed of a phase-locked loop (PLL), two singlesideband (SSB) mixers, and two multiplexers (MUXs). Switched-cascode architecture with switched LC tanks is adopted in the multiplexers to ensure fast switching. A...
A novel single-chip 860-960MHz band UHF RFID reader transceiver IC is fabricated in 0.18μm CMOS technology. The transceiver consists of a compact high-linearity low-noise-figure RF front-end, a programmable analog baseband for Rx path; and an image reject filter, a PGA, a switchable up-conversion modulator and a driver amplifier for Tx path. The 3-bit 3rd-order DSM fractional-N frequency synthesizer...
A wide tuning range LO generation architecture for software defined radio is presented. A dual VCO approach followed by a programmable divider chain based on high-speed dynamic CMOS latches provides full rail-to-rail operation with low power consumption. The 1.2 V 90 nm CMOS implementation achieves a VCO tuning range between 6 to 13.6 GHz for a power consumption between 3.5 to 13.4 mW and phase noise...
A fast-locking wideband CMOS frequency synthesizer for reconfigurable wireless applications is presented. An analog coarse tuning loop with a large loop bandwidth is used for fast locking, and new adaptive loop filters are proposed to stabilize the coarse tuning voltage when the loop is switched off. The frequency synthesizer with a 1.95-2.6 GHz frequency range is fabricated in 0.18 μm CMOS process...
An embedded 14-bit 1-GS/s digital-to-analog converter for direct digital frequency synthesizer (DDFS) application is presented. The DAC is implemented using a segmented current-steering architecture, with the top 6 bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated...
A wide-band frequency synthesizer architecture for software defined radio applications is presented, based on a dual-VCO SigmaDelta phase locked loop (PLL), with a wide-range modulus programmable divider. The design combines high flexibility to cover several wireless standards, with a scalable implementation, exploiting the capabilities of advanced digital technologies at reduced area costs. The prototype...
Low static phase offset is desired in Phase Locked Loops (PLL) employed in high speed I/O interfaces and frequency synthesizers. In this work, non idealities in phase frequency detector and charge pump contributing to static phase offset have been studied and their relative contributions analyzed in detail. A new charge pump architecture with reduced mismatch between Up and Dn current sources has...
A nonlinear sine-weighted digital-to-analog converter (DAC) can significantly reduces the power consumption and the complexity of direct digital frequency synthesizers (DDFSs). With the sine conversion implemented in the DAC, the phase-to-amplitude mapping (PAM) stage can be totally eliminated, thus drastically reduces the latency and increases the speed of the DDFS as the PAM stage is usually the...
In this paper, a wideband LC VCO with small Kvco fluctuation for RFID synthesizer application is designed using SMIC 0.18 mum standard CMOS process. The switched capacitor array and switched varactor array are used for wideband design. The VCO exhibited Kvco fluctuation of only 29%, which is about one third that of a conventional VCO. The simulation results show that the tuning frequency range is...
In this paper we present the design for a fast hopping frequency synthesizer with sub-10 ns switching time capability. The synthesizer utilizes injection-locking to obtain the fast lock time. The measurement results from a prototype design fabricated in 0.13-mum CMOS, shows good agreement with theoretical results. Minimum frequency hopping time at 3.3 GHz is 4 ns while the worst case is 10.02 ns....
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Dual-modulus prescalers based on programmable injection-locked frequency dividers (ILFDs) are presented. With a multi-phase injection, variable division ratios are obtained by simply switching different number of input signals. Implemented in a 0.18 mum CMOS process, the 4/5 dual-modulus prescaler achieves an operating range of 1.8-6 GHz with 0.22 mW measured power consumption from a 1 V supply. Based...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
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