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This paper focuses on and analysis and design of current starved voltage controlled ring oscillator. The analysis includes effect of delay time, phase noise, layout area, technology etc. on the frequency of oscillation at various power supplies and control voltages. The simulation results shows that the circuit has higher tuning range and low power consumption suitable for various application domains...
We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bitcells is completely eliminated and the power dissipation in half-selected columns is significantly reduced...
Process variations and circuit aging continue to be a main challenge to the power-efficiency of VLSI circuits, as considerable power budget must be allocated to cushion timing variations. A design-time allocation implies a uniform power spending on all fabricated instances, even if many instances do not have strong variations. Adaptive design provides a power-efficient approach to variation tolerance,...
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design shows an improvement of upto 58.63%, 55.7%...
This paper presents a behavioural model for fast DLL simulations. The behavioural model includes a modelling of the various noise sources in the DLL that produce output jitter. The model is used to obtain the dependence of the output jitter versus the power consumption. The model exploits the open-loop DLL analysis to reduce simulation time when compared to typical DLL evaluation.
VLSI circuits of 45 nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the...
This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a ΣΔ modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay...
Digitally programmable delay elements (DPDE) are required to be monotonic and low power. In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror together with a feedback technique enables a current-on-demand operation. To avoid direct currents in the output transistors, an extra inverter is introduced to independently...
Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following...
Read stability has been considered one of the dominant factors governing the overall performance and operation limitation of static random access memory (SRAM). Furthermore, periodic precharge in read/write (R/W) cycle is the major source of power consumption in an SRAM circuit. To address these two concerns, a newly developed SRAM architecture, with specific concentration on read operation, is described...
This paper presents a general purpose adaptive stimulator that can create charge-balancing current pulses from an input current signal of arbitrary waveform, amplitude and period. The stimulator is based on a new methodology of output voltage control to achieve charge balance. The stimulator was designed using AMI 0.5 mum process and operates at a supply voltage of plusmn 1.5 V. The simulation results...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
This paper presents the design of a wide band two-stage CMOS voltage-controlled ring oscillator based on the Maneatis cell. The VCO is designed for a frequency synthesizer module that generates local oscillation (LO) frequencies over a large bandwidth, targeting a multi-band acquisition system. The goal is a wide operating frequency tuning range of 400 MHz - 1.4 GHz in the VCO with low power consumption,...
This paper presents the design of a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is designed to operate as a module of the frequency synthesizer in a PLL to generate the local oscillator (LO) of a multi-band acquisition system, providing quadrature output. The goal is a wide operating frequency tuning range of 440 MHz-1.4 GHz in the VCO with low power consumption,...
This paper addresses modeling and control issues related to practical high-frequency digital PWM control of constant-frequency boost, buck-boost and flyback converters. Discrete-time models, including the effects of A/D sampling and delays in the digital control loop, are derived for two cases: output voltage A/D sampling during transistor off time in combination with trailing-edge (TE) DPWM, and...
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