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With the advent of portable and high density microelectronic devices, the minimization of power consumption in CMOS VLSI circuits is becoming a critical concern. An embedded system is a combination of electronic hardware and software and sometimes additional parts designed to perform a dedicated function. In many cases system (microprocessor) must monitor the amount of power it uses and take appropriate...
This paper presents a low-power design technique (LPDT) for a low-voltage pipelined microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPDT, a pipelined MIPS microprocessor circuit having 220,000 transistors with 5 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to...
In the recent years, the main concern of VLSI Engineers is on the power reduction techniques. In this paper, Dynamic Voltage Frequency Scaling (DVFS) for reducing power using Virtex 5 FPGA Kit along with XPower Estimator tool is used. In proposed DVFS technique, multiplication and addition are performed at different frequencies. Using sequential multiplier, practical analysis has been carried out...
This paper presents a power consumption optimization methodology (PCOM) for low-power/ low-voltage single-cycle microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques. Based on the optimization methodology with the dual-threshold techniques, a 32-bit single-cycle MIPS microprocessor design has been optimized in terms of circuit design using dual-threshold HVT/SVT CMOS devices....
With technology scaling, lower power operation has become one of the key areas of importance in VLSI Design. Power reduction in memory circuits with a little compromise on performance is very useful as they form a major part of a digital chip. This paper presents a power analysis model for adiabatic SRAM. The adiabatic SRAM's and the proposed model power characteristics are simulated, analyzed and...
In this paper, an ultra low power and low jitter 12bit CMOS digitally controlled oscillator (DCO) design is presented. Based on a ring oscillator implemented with low power Schmitt trigger based inverters. Simulation of the proposed DCO using 32nm CMOS Predictive Transistor Model (PTM) achieves controllable frequency range of 550MHz~830MHz with a wide linearity and high resolution. Monte Carlo simulation...
A low power dual-supply dual-ground voltages domino circuit is presented in this paper. The domino circuit employs a high ground voltage and the shared-well technique to improve the dual-supply voltage technology and further reduce the power consumption and optimize the layout area. Based on Chartered 0.35 um 2P4M CMOS technology, simulation results shows that dual-supply dual-ground voltages domino...
An 8-core SPARC64™ VIIIfx processor is fabricated in a 45nm CMOS process and achieves a peak performance of 128GFLOPS. Measured results show that the processor consumes only 58W of power when executing a maximum power program. Fine-grained power analysis was used to tune the micro-architecture for low power consumption, and circuit-level low-power techniques were developed. Water cooling and supply...
This paper presents an improved circuit design of low power 1-bit full adder circuit. The circuit is designed and implemented based on top-down approach using total number of 10 transistors, thereby, known as 10-T cell. After simulation of the circuit, a clear view of the circuit performance, in terms of power, delay, area was studied. The performance of the proposed circuit was compared with other...
Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many emerging applications can tolerate computational errors caused by hardware unreliabilities, at least during certain execution intervals. In this paper, we propose scalable stochastic processors, a computing platform for error-tolerant...
This paper proposes a CMOS comparison architecture for low-power pre-computation-based content-addressable memory (PB-CAM). Instead of conventional architecture, we implement ours by CMOS logic gates to eliminate power consumption induced by short-circuit current. We use TSMC 0.18-??m techfile to estimate the power consumption by Synopsys Nanosim. The width ratio between PMOS and NMOS is set as 3:1...
This paper presents a low-power 5-bit 1.35-GSPS current-steering digital-to-analog converter (DAC) for ultra-wideband (UWB) transceivers. A “3 (thermometer) + 2 (binary)” segmented structure is used for reaching a compromise between the circuit complexity and differential nonlinearity (DNL) error. To save the power consumption while maintaining the same output voltage swing, a bipolar current source...
We report a pixel-block scanning image segmentation VLSI based on a region-growing approach. Using the two techniques of (i) a limited scan to the boundary of each grown region and (ii) continued block-internal region growing, we have improved the overall segmentation speed and power consumption in comparison to a previous design. We evaluated the segmentation performance by MATLAB simulation and...
Based on the observation that dynamic occurrences of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor SRAM cell (4T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
The power consumption and the matching will be the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present the SON technology, leading to the simple fabrication of sustained mono-Si nano-membranes over an empty tunnel, and discuss on the application of this process to build-up electronic devices...
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