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Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper presents a new SAT-based Automatic Test Pattern Generation (ATPG) approach targeting transition delay faults using a novel 8-value encoding system. Experimental...
Small delay defect (SDD) ATPG has been around for a few years now; however, its adoption is not prevalent due to various reasons. (i) Unique detection with SDD ATPG patterns over transition delay fault (TDF) ATPG patterns is often not easy to establish due to the large volume of the former and the insistence on coverage due to the latter. (ii) Lack of a seamless method to target SDD patterns for nodes...
Functional timing analysis (FTA) overcomes the limitation of static timing analysis (STA) to allow distinction of false and true paths. Modern FTA methods exploit timed characteristic functions (TCFs) to implicitly calculate the longest true delay of a circuit. However, they are inadequate for the verification of timing exceptions, which is crucial for timing signoff, due to their implicit enumeration...
This paper presents a third order continuous-time (CT) delta-sigma (ΔΣ) modulator with a fast three-level feedback scheme. The proposed technique uses two decorrelated 1-bit quantisers to produce a three-level feedback signal without requiring a decoder in the feedback path thus enabling high-speed operation. An efficient dynamic-element matching technique is also implemented to mitigate the weak...
The paper presents a new graphical platform for automatic test patterns generation and fault simulation for digital circuits. The platform integrates two existing academic tools for test pattern generation and fault simulation: ATALANTA and HOPE. Both tools use a specific format "bench" for circuit description which is not suitable in connection to professional CAD tools. Therefore, the...
A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has fault effects similar to a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. In this paper we present an efficient test and diagnosis...
This paper proposes a complete method of diagnostic test generation for transition faults. The method creates a diagnostic test generation model for a pair of transition faults to be distinguished from a given full-scan sequential circuit and employs an ordinary transition fault ATPG tool. The proposed model supports launch-off-capture and launch-off-shift modes which is supported by the ATPG tool...
Diagnosis of integrated circuits is an arduous process. Tools are needed which aid developers locating circuit's faulty parts faster. In this work path delay faults are considered. A simulation based diagnosis algorithm using diagnostic test patterns is introduced for locating the cause of the delay fault. Initial paths are segmented to improve the diagnosis accuracy. For each segment, additional...
A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware...
With technology scaling, the growing impact of signal integrity issues imposes significant challenges in integrated circuit testing. They cause delay in the supply and ground networks, cross talk noise between multiple interconnects, variations in substrate and thermal noise parameters of the circuit, etc. Therefore, the consideration of signal integrity issues during pattern generation ensures a...
It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling a so-called SAT solver to compute a test. More recently, the potential of SAT-based ATPG has been significantly extended. In this paper, we first provide introductory knowledge on SAT-based ATPG...
A GPU-based timing-aware ATPG is proposed to generate a compact high-quality test set. The test generation algorithm backtraces and propagates along multiple long paths so that many test patterns are generated at the same time. Generated test patterns are then fault simulated and selected. Compared with an 8-core CPU-based timing-aware commercial ATPG, the proposed GPU-based technique achieved 36%...
Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
Delay testing is performed to guarantee that a manufactured chip is free of delay defects and meets its performance specification. However, only few delay faults are robustly testable. For robustly untestable faults, non-robust tests which are of lesser quality are typically generated. Due to significantly relaxed conditions, there is a large quality gap between non-robust and robust tests. This paper...
Today's digital circuits demand both high speed performance and miniaturization of chip size. As a result, delay fault testing has become very important to verify the quality requirements of VLSI chips. Full scan has been used to generate test patterns that achieves high fault coverage, of which the standard techniques for delay scan testing are skewed-load and broad-side. However, as the circuits...
A multi-cycle (or multi-pattern) scan-based test consists of several primary input patterns, which are applied consecutively in functional mode, between scan operations. Multi-cycle tests can reduce the total number of cycles needed to achieve a target fault coverage. Additionally, such tests exercise the circuit in its functional mode of operation during several clock cycles where the primary input...
Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique...
Testing for small-delay defects requires fault-effect propagation along the longest testable paths. However, the selection of the longest testable paths requires high CPU time and leads to large pattern counts. Dynamic test compaction for small-delay defects has remained largely unexplored thus far. We propose a path-selection scheme to accelerate ATPG based on stored testable critical-path information...
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can...
Test patterns of path delay faults (PDFs) are usually generated with static or robust sensitizing criteria for side inputs of gates, because defects affecting the delays of the PDFs will be captured by these patterns unconditionally. However, under functional sensitization (FS), there exist a class of defects that can be tested unconditionally, if they are not masked by the off-input controlling values...
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