Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Most of the applications require hard real time signal/data processing potentiality for which fast and dedicated VLSI architectures are the best solution. But designing such circuits lead to high occurrences of failure in the system. Hence there is a critical need for fault tolerance techniques for VLSI designs to increase the reliability of the system. Redundancy techniques are implemented widely...
Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work...
Triple modular redundancy (TMR) is a well-known technique for building fault-tolerant systems. In TMR, a module unit is triplicated, and the outputs of these three units are compared by a voter. In this paper we consider systems that consist of multiple TMR units in series. Only recently has it been found that even such simple systems can be configured into various structures. We propose (i) a method...
Due to aggressive scaling, reliability issues influence the design process of integrated circuits more and more. A well known technique to tackle these issues represents Triple Modular Redundancy (TMR). It strongly improves reliability of a design at the expense of at least tripled area and power consumption. In this contribution, we propose an enhanced TMR approach that significantly decreases the...
Module redundancy is often used as a method of construction a reliable system. TMR is used as the method of improving reliability by module redundancy. However, TMR does not decide correct result when two of three modules fail. Therefore, we proposed a new architecture of voting termed as Stateful TMR. It uses the result of TMR and State of the history, to select the most reliable module. By the simulation,...
According to the high-reliability requirement of emergency trip system (ETS) for steam turbine, a triple modular redundant ETS system is presented in detail in this paper. The system consists of groups of input modules gathering data from sensors, system bus, main controllers running the same application program, and groups of output modules, all of which are configured to triple hardware redundancy...
We consider systems comprised of multiple triple modular redundancy (TMR) units in series. Only recently have researchers found that even such simple systems can be configured into various structures. We develop an algorithm for finding a structure that maximizes reliability. Using this algorithm we show that new structures have optimal reliability within some ranges of voter and module reliability.
Nanoelectronic systems are extremely likely to demonstrate high defect and fault rates. As a result, defect and/or fault tolerance may be necessary at several levels throughout the system. Methods for improving defect tolerance, in order to prevent faults, at the component level for QCA have been studied. However, methods and results considering fault tolerance in QCA have received less attention...
A triple module redundant turboset emergent trip system (ETS) based on triple modular redundancy fault-tolerance technology is discussed in this paper, which is used for safety protection of large steam turbine. The system consists of input modules, main controllers, bus controllers and output modules, in which the 2-out-of-3 (2oo3) vote mechanism is adopted to enhance the reliability and safety of...
This paper describes an efficient approach of applying mitigation to an FPGA design to protect against single event upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on their importance within the design. Higher priority is given to structures causing "persistent" errors within the design. For certain applications, applying selective mitigation...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.