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Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1-3] and OOK modulation enables ultra low power (ULP) consumption...
This paper presents a new multi-conversion super heterodyne architecture for 60GHz broadband wireless application. The proposed design consists of a three-stage conversion with the help of a 24GHz VCO and a divider. The local oscillator frequency stands far away from RF and both IF signals reduce inter-modulate interference. The first and second mixers sharing the same 24GHz VCO relax the complexity...
In this paper, an ultra low-power wideband frequency synthesizer is demonstrated in a 90-nm CMOS technology. The circuit is intended for low data-rate sub-GHz transceivers and is based on a programmable integer-TV phase-locked loop. The frequency synthesizer in cooperation with divide-by-two frequency dividers is able to provide quadrature LO signals in the 300-470 MHz and 750-950 MHz RF bands with...
This paper explores where MEMS devices such as BAW and low frequency silicon resonators can be used to reach further miniaturization and to lower the power dissipation of 2.4GHz transceivers targeting BAN and WSN applications. The system requirements for improving such networks are derived after analyzing appropriate low power communication protocols. A super-heterodyne transceiver architecture taking...
The following topics are dealt with: medical and vision processors; ultrawide band circuits; SRAM variability; clocking building blocks; analog circuits; advanced transceiver techniques; high speed on-die network processor clocking; RF and new wireless transceivers; advanced SRAM circuits; advanced clock generation; digital circuit resilience;low power memory and interface techniques; PLL and CDR;...
This paper presents a phase-locked loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in the UMC RF 0.18 mum CMOS process. The PLL produces a set of different 16 digitally programmable frequencies in the [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback...
New design techniques are needed for ultra-low-power battery-operated CMOS transceivers with ever-shrinking minimum feature sizes and power supply voltages. A fully-integrated low-IF receiver front-end for GPS applications is presented that addresses this challenge. Integrated in 0.13 mum CMOS, its key attribute is ~3X lower power than any previous design: The RF front-end, PLL, IF amplifiers and...
This paper presents key design techniques and challenges in implementing one of the first integrated, energy-efficient 60 GHz transceivers including baseband circuitry. The 90 nm CMOS direct-conversion design operates from a 1.2 V supply and has been optimized for 5-to-10 Gb/s QPSK modulation centered at 60 GHz. To achieve power consumption of 170 mW in transmit mode and 138 mW in receive mode, this...
This paper proposes a new stable design strategy for 1-bit high order digital DeltaSigma modulator used as division controller for multi-standard fractional-N frequency synthesizer. This digital DeltaSigma modulator presents simplicity and low power consumption. Simulation results illustrate the DeltaSigma modulator good performances in terms of spectrum purity and accuracy.
An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply
A 3.125GHz PLL fabricated in a 0.13 /spl mu/m CMOS process in a area of 0.064mm/sup 2/ is described. The PLL uses an architecture optimized for low noise, low power and small die area. In steady-state operation, the PLL forces the up and down currents in the charge pump to match one another. The total measured jitter is 1.3ps rms when operating at 3.125GHz and the chip consumes 15mW.
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