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A novel high-κ gate stack structure with HfON/SiO2 as dual tunneling layer (DTL), AlN as charge storage layer (CSL) and HfAlO as blocking layer (BL) is proposed to prepare the charge-trapping type of MONOS non-volatile memory device by employing in-situ sputtering method. The memory window, program/erase and retention properties are investigated and compared with similar gate stack structure with...
In this work, the lateral InGaAs tunnel FET is configured and sized to enable gate control of the Zener (reverse bias) tunneling current. The p+InGaAs transistor channel is 4 nm thick with a n+p+ source injector and a thin 3/3 nm HfO2/Al2O3 high-k gate dielectric. Atomic-layer deposition (ALD) is used to deposit the gate dielectric.
The authors have fabricated silicon nanowire (SiNW) based Al2O3/HfO2/SiO2 nonvolatile-memory (NVM) cells with varying HfO2 trapping layer thickness have been fabricated by using self-aligning approach. The cells exhibit excellent characteristics such as fast programming/erasing (P/E) speeds, good endurance and excellent retention. The P/E speed is not sensitive to the HfO2 layer thickness. The magnitude...
The effects of stress polarity in bias-temperature instability (BTI) tests on high-?? gate dielectric stacks were studied based on the distribution of interface traps and bulk traps extracted by modified charge-pumping (CP) techniques. The bipolar bias-temperature instability were compared between MOSFETs with HfO2/LaOx and HfO2/AlOx dielectric stacks. From the results of interface trap density (N...
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