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In this contribution, we present a coverage driven functional verification environment based on the UVM framework and the System Verilog language to certify the operational correctness of the ECC error management logic used in volatile and nonvolatile memories. We apply this methodology to floatinggate nonvolatile memories for the embedded market, which requires a read error rate of 10−14. The proposed...
This paper describes the design and implementation of an End-to-End digital wireless communication system (E2E) system on the Zynq-7000 Field Programmable Gate Array (FPGA) and Evaluation Development (Zed) Board with an Analog Devices AD9364 Wideband Transceiver from a model-based design system. Furthermore, the paper presents the design path to reconfigure the software controlled logic blocks for...
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The...
Content protection relies on several security mechanisms: (i) encryption to prevent access to the content during transport, (ii) trusted computation environment to prevent access during decoding, and we can also add (iii) forensic watermarking to deter content re-acquisition at rendering. With the advent of next generation video and the ever increasing popularity of embedded devices for content consumption,...
To address the high level of dynamism and variability in modern streaming applications (e.g. video decoding) as well as the difficulties in programming heterogeneous MPSoCs, we propose a novel execution model based upon both dataflow and Kahn process networks. This paper presents the semantics and properties of this hierarchical and parametric model, called DKPN. Parameters are classified and it is...
To address the high level of dynamism and variability in modern streaming applications (e.g. video decoding) as well as the difficulties in programming heterogeneous MPSoCs, we propose a novel execution model based upon both dataflow and Kahn process networks. This paper presents the semantics and properties of this hierarchical and parametric model, called DKPN. Parameters are classified and it is...
This paper presents a new technique capable of predicting the processing time of video decoding tasks. Such technique is based on the collection and transmission in the compressed video bit-stream, of a suitable statistic information relative to the decoding process. Simulation results show that very accurate decoding time predictions can be obtained without the need of the actual decoding. These...
Error correcting code (ECC) is an essential method in protection of NAND Flash memories. Complexity of it is increasing rapidly with the increment of error correction capability. Traditionally, the software implementation of ECC which has less cost and high flexibility is nearly ignored due to its inefficiency. This situation can be changed by design of faster software-based ECC scheme. We have found...
Forward Error Correction (FEC) consumes excessive computation in a Software Defined Radio (SDR) system. In this work, a high-throughput flexible FEC processor is proposed for the decoding acceleration. The FEC processor enables Turbo/QC-LDPC/Convolutional Code decoding with software-hardware co-reconfigurability. A multi-algorithm unified trellis processing unit is introduced for resource sharing...
The complexity of high performance digital systems has rapidly increased. When we design such systems in a system-on-chip (SoC), lots of predesigned intellectual properties (IPs) are integrated to build a system. To verify the functionality of such systems, conventional simulation methods take extremely long time and they have limited debugging capability due to the existence of many predesigned IPs...
This paper presents Open-PEOPLE, a hardware and software platform which aims to widen access to accurate power consumption measurement to the scientific community. The idea behind this platform is to centralize and abstract the instrumentation effort and the investment cost then allow geographically remote users to make power measurement remotely without requiring any specific costly hardware and/or...
Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads (up to 50% area of the overall platform). As a solution to this problem researchers have employed statistical...
There are ongoing efforts to enable development and optimization of hardware and software simultaneously. It is believed that the most effective solution is a system-level virtualization based on a virtual model. This paper proposes a multi-level virtual model of our 32-bit RISC Aldebaran AP with support for several features that further enhances system development efficiency.
Hardware accelerators are widely employed to alleviate CPU's burden in video applications. Playing high definition videos encoded in popular standards such as H.264, MPEG4 and VC-1 has already gain significant speedups on Intel, AMD and NVIDIA platforms. In this paper, we realized fluent playback of 720p AVS video on the Godson Platform. We made that possible by expanding the VA-API (Video Acceleration...
Dynamic Partial Reconfiguration allows to dynamically change the behaviour of a portion of the FPGAs by downloading new information in the configuration memory of the device. Since modern Systems-on-Programmable-Chips (SoPCs) make extensive use of this feature, many reconfigurable area are placed in the device, with several configurations for each area. This comes at a cost in terms of dependability...
The design of specialized hardware for Network Intrusion Detection has been subject of intense research over the last decade due to its considerably higher performance compared to software implementations. In this context, one of the limiting factors is the finite amount of memory resources versus the increasing number of threat patterns to be analyzed. This paper proposes an architecture based on...
This paper proposes a digital public address (PA) system which is capable of multi-zone and text-to-speech (TTS) broadcasting functions for campus broadcasting and language listening training/exam. The proposed digital PA system can achieve environmental broadcasting requirement which means different broadcasts for different zones at the same time. On the other hand, it cannot cause noise to other...
Multi-core platform has become a trend in hand-held embedded systems, such as smartphone and tablet. To improve the video decoding performance by using the multiple cores, one of parallel algorithms should be adopted. However, different parallel algorithm should be selected for different video standard on different platform. Therefore, an engine to estimate performance on a target platform from existing...
The modern satellite signals have improved their bit transmission robustness with adding new protection methods like block-interleaving and Forward Error Correction. While these methods provide clear improvement in challenging environment, the implementation of the decoders on receiver side adds more complexity. In this paper we introduce efficient methods for block de-interleaving and for Viterbi...
The increasing complexity of the current and future system-on-chip designs poses enormous challenges to system-level design. The uniform SystemC co-simulation methodology is proposed to describe the whole chip entirely with the same language. Elimination of the interaction between different simulators brings significant speedup in co-simulation. The processor model divides every instruction into a...
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