Dynamic Partial Reconfiguration allows to dynamically change the behaviour of a portion of the FPGAs by downloading new information in the configuration memory of the device. Since modern Systems-on-Programmable-Chips (SoPCs) make extensive use of this feature, many reconfigurable area are placed in the device, with several configurations for each area. This comes at a cost in terms of dependability of the system and of memory occupation. The proposed methodology focuses on increasing the dependability of partially reconfigurable systems by safely storing compressed configuration data inside the FPGA