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The 1588 Precision Timing Protocol (1588-PTP) states that a timestamp event is generated at the time of transmission and reception of any event message and that the timestamp event occurs when the message's timestamp point crosses the boundary between the node and the network (event generation points). The protocol defines the message timestamp point for an event message as the beginning of the first...
We present Timestamp Order Preserving (TOP), a replicated state machine (RSM) protocol that exploits the synchrony of networks to provide high performance. TOP uses physical timestamp of synchronized clock as a consistent total order to achieve consensus. It keeps estimating the bounds of network latency and offset of synchronized clock to deduce the commit time for each operation. It adopts speculative...
The latest IEEE WLAN 802.11ad standard guarantees the multi giga bit throughput which is highest in the Wireless LAN (WLAN) technology. The system designed for such high performance will pose enough design challenges to make them consume low power. This can however be achieved by adopting low power management and control block in the digital part of the System on Chip (SoC) like Medium Access Control...
We consider the design of a shared global on-chip communication medium using repeated equalized transmission lines (RETLs). Our design overcomes a number of limitations with previously proposed shared global mediums based on transmission lines. Prior solutions require wide-pitch transmission lines that occupy considerable area, do not support multicast or broadcast operations, and employ centralized...
To study dynamic aspects of network protocols, like the transmission network protocol TCP, and networked control systems (NCS) with a UDP-like flow in a single framework, we employed UPPAAL, a tool that simulates discrete event systems as switched automata. Delays and packet losses can degrade the performance of a control loop, leading in the worst case to instability. In opposition to standard communication...
We build upon the clean-slate, holistic approach to the design of secure protocols for wireless ad-hoc networks proposed in part one. We consider the case when the nodes are not synchronized, but instead have local clocks that are relatively affine. In addition, the network is open in that nodes can enter at arbitrary times. To account for this new behavior, we make substantial revisions to the protocol...
This work proposes an integrated remote terminal and bus controller: MIL-STD-1553+, implemented in 1.2 V 65-nm CMOS technology occupying 115470 μm2 of area. It incorporates a synchronous back-end and host processor interface to a true dual port memory for faster memory accesses. Employing a majority-based sampling free-running decoder at its front-end and scaled-up protocol state machines in its control...
Rapid improvements in integrated circuit technology over the past few decades enable increasingly large and complex Field Programmable Systems-on-Chip (FPSoC). Due to the large number of components used, the traditional bus-based interconnect scheme becomes cumbersome and restrictive. Hence, the Network-on-Chip (NoC) interconnect paradigm becomes appealing due to its many advantages such as scalability...
This work proposes a MIL-STD-1553B remote terminal controller: RT-MIL-STD-1553+, which processes data rates of 100-Mb/s over 1553 buses. This redesigned controller has three major architectural enhancements over the current 1-Mb/s controllers. Firstly, it incorporates a synchronous back-end and host processor interface to a true dual port memory to enable faster memory accesses. Secondly, the controller...
Packet classification is a network kernel function that has been widely researched over the past decade. However, most previous work has only focused on achieving high-throughput without considering its energy-efficiency implications. With the rapid growth of Internet, energy-efficiency has become an important metric for networks. We present the design of an energy-efficient packet classifier on Field-Programmable...
Software development becomes an important issue in today's MPSoC design. Due to the inherent non-deterministic behavior of MPSoCs, they are prone to concurrency bugs. Debugging tools for MPSoC may be grouped in the following classes: simulators, parallel software development environments, NoC debuggers. An important gap is observed concerning a complete NoC-based MPSoC: tools to inspect the traffic...
10Gbps Ethernet Security Processor is very important in future network telecommunication. In order to meet the performance of ultra high throughput of 10Gbps ESP, An architecture of multiple SHA-1 IP cores paralleled based crossbar switch are proposed in this paper. Firstly, An ultra high throughput, low power consumption SHA-1 algorithm IP-core are designed, then, an effective scheduling architecture...
Task migration is a well-known strategy adopted in distributed systems for load balancing. but the adoption of such strategy in NoC-based MPSoC is scarce in the literature. This paper proposes a complete task migration protocol for NoC-based MPSoCs. The migration transfers the task code, data and context to another PE. The paper presents the communication strategy to ensure coherence in the messages...
The expressive power of regular expressions has been often adopted in network intrusion detection systems, virus scanners, and spam filtering applications. However in the CPU based systems, pattern matching is one of the most computation intensive parts. In this paper, we present the design, implementation and evaluation of a regular expression string matching programmable controller (SMPC). This...
Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet...
A SerDes (Serializer/Deserializer) is a key component for high speed serial communication. Networks architectures and point to point communication links are vital building blocks for space-based high-speed communications and sensor data access. Honeywell has enabled optimized space communication systems with both its SerDes standard parts and its SerDes macro-cells that are part of the HX5000 Rad-Hard...
FPGA-CF is an open-source, portable, extensible communications package that consists of a small hardware core (less than 600 slices) and and a host-software library/API. It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard internet protocols. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all...
The LTE standard supports a maximum throughput of 300MBit/s using 4×4 MIMO and a channel bandwidth of 20 MHz. At the same time the latest HSDPA technology supports 82MBit/s using 2×2 MIMO and Dual Cell techniques. While LTE uses a conflict-free interleaver, which allows highly efficient implementation of parallel decoders for such throughputs, HSDPA uses the UMTS interleaver that causes memory access...
This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces...
Most scheduling based latency insensitive designs in the literature focus on systems whose graphical representation is a single strongly connected component (SCC), where a hand-shake based protocol can be replaced by periodic clock gating through ASAP scheduling. However, for systems that are represented as interconnected SCCs, `back pressure', always implemented as the `stall' signal in the backward...
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