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Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low supplies. This paper evaluates the Static Noise Margin...
Vertical GaN power semiconductors promise higher power with faster switching speeds but the development of this technology has been slowed. This is due to the expense and lack of familiarity with GaN substrates. This paper will detail the functionality of HRL's cutting-edge vertical GaN transistor which is mounted onto a specially made PCB and tested. The testing consists of a static characterization...
An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
Scaling in CMOS has increased the attainable operational frequencies, while greatly increasing the transistor's parasitic modeling complexity. Additionally, the performance of the ever-smaller on-chip passives for mm-wave and THz circuits is being degraded by numerous process requirements and limitations, such as high densities of dummy metals. This work discusses the main transistor layout trade-offs...
A novel structure for an analog linear variable gain amplifier (VGA) fabricated in CMOS 0.35μm technology is proposed in this paper. In order to increase noise performance and linearity, the VGA is designed based on differential topology. The pseudo-exponential gain is altered following the control of a current source supplied to a differential source-coupled pair with diode-connected loads. This...
Source gated transistors (SGTs) are field effect devices with operating characteristics desirable for both analog and digital operation. Unlike in conventional transistors, the length of the source electrode, S, may play an important role in the behavior of SGTs. Optimizing the source region geometry according to mode of operation (dominant mechanism of current injection) leads to larger saturated...
Achieving large low-frequency gain together with low noise and a high unity-gain bandwidth (UGB) imposes conflicting requirement on bias currents in single stage operational transconductance amplifiers (OTA). In this work, we propose a modified biasing scheme for folded cascode OTAs to de-couple the gain versus noise/UGB trade-off. The effectiveness of proposed biasing scheme is illustrated with the...
In this paper, low cost 1200V UHV LDMOS device has been proposed. As BVD and Ron are contradictory, so to make low Ron, high breakdown voltage is the challenge of this paper. The key feature of this device is the linear P-top which is used to obtain best charge balance, and increase the diffusion current to move faster in the drift region which reduces the electric field and substantially helps to...
Broadband impedance matching for band-pass RF power amplifiers targeting Software Defined Radios (SDR) is reviewed with emphasis on the power supply voltage and how higher voltage operation could improve power versus bandwidth. Measured data on a 100 watts CW GaN amplifier operating at 100 V over the 500 MHz–2 GHz frequency band are shown to support the analysis. Results show that amplifier operation...
This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of...
A charge pump is DC/DC converter that produces a higher output voltage than power supply or generates a negative output voltage. Some variants of charge pumps work as voltage regulator, too. A charge pump is realised by capacitors, transistors and/or diodes. Therefore, some charge pumps are integrated directly to the systems that use these charge pumps. E.g. Flash or EEPROM memories are supplied from...
In this work a dynamic biasing circuit for current conveyor (CCII) applications is proposed and discussed with circuitry details. This solution, applied for the first time to current-mode circuits, allows to decrease the steady state power consumption of the considered circuit, minimally affecting its performance. The dynamic biasing solution here conceived is able to sense the input signal providing...
Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized...
The mathematical model of the microelectronic device for measuring petroleum products humidity which allows to define value of the voltage or current in any point of the circuit during the definite moment of time is designed. Based on the mathematical model of the microelectronic device for measuring petroleum products humidity the dependences of transformation function and equation of sensitivity...
This paper presents a robust CMOS Miller operational amplifier (OpAmp) that has high immunity to electro-magnetic interference (EMI). The proposed robust CMOS Miller operational amplifier uses the modified replica Miller OpAmp concept with the source-buffered Miller OpAmp with source degeneration resistance in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz)...
A digitally controlled LDO in 14nm tri-gate CMOS powering an Atom™ core with embedded power gates enables per-core DVFS over a wide voltage-frequency range. The LDO demonstrates 99.6% peak current efficiency at 2.5A load current and provides a power density of 26.1 W/mm2. The multi-mode digital controller featuring non-linear mode and adaptive gain achieves <20ns settling time with a 100mV droop...
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
A low-dropout regulator (LDO) with 800 mA load current with wide range input voltage is designed and proposed in this paper. The designed LDO includes two cascaded LDOs. The first one uses a p-type of DMOS power transistor to convert a wide input voltage (3.9 to 20 V) to a stable output voltage of 3 V, which provides a supply voltage for other circuits. The second LDO is designed to achieve a large...
This paper presents a technique for the fault-based test of the analog amplifiers. The circuit defects are modeled with the 2-fault transistor models. The test method combines the amplifier evaluation both in and out of the normal operating region, with the transconductance of the amplifier being the key test parameter. Furthermore, the additional low current test is employed in order to maximize...
The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated...
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