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In this paper an efficient fused three operand floating point add-subtract unit is designed using Binary Signed Digit (BSD) adder. BSD adder-subtractor improves overall speed of addition due to its carry limited operation. BSD adder delay reduces by 28% and 17% compared to carry save adder (CSA) and ripple carry adder (RCA) respectively. Three operand adder performs two additions in a single unit...
FIR filter is significant unit in digital signal processing (DSP). In this paper a reconfigurable architecture named as modified constant shift method (MCSM) is proposed. The architecture uses the concept of compressors to make the FIR filter more power efficient. This compressor based adder-tree architecture is capable of working for different word lengths of FIR filter coefficient with less hardware...
This paper presents a procedure to optimize modular multiplication by constants. Such operations have been demonstrated to be crucial to design efficient reverse converters, which are the bottleneck of RNS. The focus of this work is the use of Residue Number System (RNS) moduli sets without limitation of the number of channels, which are useful for Digital Signal Processing (DSP) applications. Moreover,...
This paper presents the implementation of the novel FIR filter with the filter architecture using shift and add multiplier. The designed is compared to the previous novel FIR designs such as Direct form and previous shift add architecture in Direct form and Transposed form. The design is done on the Transposed structure form of FIR as it is desirable in low power applications. The filters are optimized...
In the recent times we see that the digital signal processing applications are increasingly becoming complex which leads to the extensive using of the floating point numbers in the hardware processing implementations. In this paper, we will focus on the various advantages the HUB technique has when implemented on FPGA applications. The one advantage which the HUB floating point technique has that...
The trade-off between speed and power consumption has become a critical concern as process technology make in-roads to 40nm proximity in modern VLSI technology. We can reduce this trade-off by compensating with accuracy i.e. if an application like Digital signal processing (DSP) can accept some errors then a large power can be saved and at the same time speed can be enhanced. In this paper, we propose...
This paper describes the implementation of a high throughput FFTs implemented on FPGAs, using a modified version of the Radix 2N architecture. The implementation uses a synthesis method which supports “super-sampling” to provide very high throughput. Special vector structures in the tools and hardware architecture are supported where complex vectors form the input on each clock cycle, and multiple...
In this paper, we propose an area efficient adder based reverse converter for a recently proposed new moduli set {22n+1 − 1, 22n+1, 22n − 1}. First, we simplify the New Chinese Remainder Theorem (New CRT I) to obtain a reverse converter. Second, we further reduce the resulting architecture to obtain a memoryless reverse converter that uses three 2n bits CSAs (CSA1, CSA2, CSA3), two parallel CPAs (2n...
In this paper, Carry Select Adder (CSA) architecture are proposed using parallel prefix adder. Instead of using 4-bit Ripple Carry Adder (RCA), parallel prefix adder i.e., 4-bit Brent Kung (BK) adder is used to design CSA. Adders are key element in digital design, performing not only addition operation, but also many other function such as subtraction, multiplication and division. Ripple Carry Adder...
In this paper we propose a new architecture for an efficient MAC (Multiplier Accumulator Unit) unit with low area consumption which includes Vedic Square as an alternate component in the MAC unit. Vedic Square is based on the principle of Duplex property of Urdhva Tiryagbhya. Using the proposed architecture, 50% of logic gates are reduced from the basic level of 2*2 bit and 12.64% from 16*16 bit square...
In Public Key Cryptography, the most costly arithmetic operation is first inversion then multiplication. There aren't big researches concerning modular inversion, it exist two famous algorithms which are Fermat and Extended Euclid algorithms. All researches are oriented to the modular multiplier, it exist a big number of methods to compute it. The goal of our paper is to present a of a 256-bits multiplier...
In the last years, research on residue number systems (RNS) has targeted larger dynamic ranges in order to further explore the inherent parallelism of these systems. In this paper, a performance analysis is presented for RNS-to-binary architectures based on New Chinese Remainder Theorem I (New CRT-I). Four different approaches are explored, each of them focused on the area or delay reduction of one...
Many Floating Point operations have been acknowledged to be useful for many real time graphic and multimedia application as well as DSP processors. Many Digital Signal Processing algorithms use Floating point arithmetic, which requires millions of calculations per second to be performed. For such stringent requirements, design of fast, precise and efficient circuits is the goal. This brief presents...
A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift...
A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift...
A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift...
Digital signal processing requires a large number of mathematical operations to be performed in high speed real time mode and repeatedly on a set of input data. The power requirements of the DSPs are increasing day by day along with the processing speed and chip area. Because of the limitation of power supply and space, mobile devices cannot use the general purpose processors to process digital signals,...
In this work, two approaches to realize a finite impulse response (FIR) filter using residue number system (RNS) are proposed. The proposed implementations take advantage of shift and add approach offered by the chosen moduli set. Both the architecture were implemented using gate level Verilog HDL and are synthesized using Cadence RTL compiler in UMC 90 nm technology. The performance of the filters...
Digital multipliers are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. But the implementation of squaring has the advantage that we can avoid the generation of many partial products used in multipliers by eliminating the redundant bits, thus resulting the...
In this work, an efficient finite impulse response (FIR) filter using Residue Number System (RNS) is proposed. The chosen moduli set offers the advantage of shift and add approach. The proposed filter architecture is compared with an earlier proposed version of reconfigurable RNS FIR filter. The filters are synthesized using Cadence RTL compiler in UMC 90 nm technology. The performance of the filters...
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