The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In smart metering systems, when the density of node is high or distance of communication range is large, the adjacent node number becomes large. If routing based on the number of hop from the sink node is used in such a network, the deviation of load will become large and it will shorten the network lifetime, also degrades other network performance. In this paper, we proposed the techniques solving...
Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results...
Topology has significant effects on the most important parameters of a network such as latency and power consumption. The sphere based topology is a new structure for Network-on-Chips that forms in sphere shape. We have used a Zone-Order label based algorithm for the routing that is a general algorithm for routing requirements, and it is based on spanning tree. We have compared sphere based topology...
This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints...
In this paper, we propose addressing schemes to optimize Area Power Timing (APT) product, utilizing data dependency in Majority Based Full Adder (MBFA) topologies. With advancement in technology and demand of portability in applications, all the design parameters of a digital design viz. Area Power and Timing requirement have become equally important. As all the three need to be as small as possible,...
This paper deals with the implementation of full adder chains by mixing different CMOS full adder topologies. The proposed approach is based on cascading fast Gate Diffusion Input (GDI) Full Adders interrupted by static gate having driving capability, such as inverter, thus exploiting the intrinsic low power consumption of such topologies. The results obtained show that the proposed mixed-topology...
Current network infrastructures exhibit poor power efficiency, running network devices at full capacity all the time regardless of the traffic demand and distribution over the network. Most research on router power management are at component level or link level, treating routers as isolated devices. A complementary approach is to facilitate power management at network level by routing traffic through...
This paper presents a Tabu search based approach for the topology synthesis of application-specific multicore architectures using an automated design technique. The Tabu search method incorporates multiple objectives in order to generate an optimal NoC topology which accounts for both power and performance factors. The method generates a system-level floorplan in each major stage of the topology synthesis...
In this paper, we present a novel approach in Networks-on-Chip topology optimization, by considering the network power consumption, packet transmission delay, and system reliability, simultaneously. We use the Particle Swarm Optimization technique to acquire the most suitable topology architecture, which achieves maximum reliability as well as minimum delay and power consumption. The optimization...
A Mobile ad hoc network is a collection of wireless nodes that dynamically organize themselves to form a network without the need for any fixed infrastructure or centralized administration. The network topology dynamically changes frequently in an unpredictable manner since nodes are free to move. Support for multicasting is essential in such environment as it is considered to be an efficient way...
On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width)...
This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous...
Due to the advanced lithography technologies in current semiconductor process, X-architecture has been widely used in VLSI physical design. The architecture contributes more improvements in clock delay, wire length, and power consumption than those of Manhattan architecture. This work proposed an X-architecture zero skew clock tree construction with buffer insertion and sizing. A pattern matching...
Wireless ad hoc networks consist of nodes which can communicate with each other in a peer-to-peer fashion over single hop or multi hops without any fixed infrastructure such as access point or base station. In flat topology there is no topology management concept and all the nodes participate in routing. In this paper the task of topology management for ad hoc networks is implemented using routing...
The paper presents a new approach for the physical design of integrated circuits where all logic cells are designed on the fly, without the limitations that exists when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). A cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS...
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging systems-on-chip (SoC) design paradigms based on networks-on-chip (NoC) interconnection architectures to 3D chip designs. In this paper, we consider the problem of designing application-specific 3D-NoC architectures...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
Sink mobility has become an increasingly important requirement of various sensor network applications. Handling such mobile sink conditions brings new challenges to large-scale sensor networking. This investigation proposed a hybrid-structure routing protocol (HSRP) that combines the benefits of grid-based and cluster-based structures. Grid-based structure is designed to solve the cluster head selection...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.