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In this paper, the power consumption of the integrated circuit is discussed. At first, take CMOS integrated circuit as an example, we analyze the source and composition of the power consumption of the integrated circuit and then, we elaborate on the optimization of the integrated circuit on system level, algorithm level and structure level, RTL level, gate level, transistor level, process level and...
Distinguished features of Particle Swarm Optimization (PSO) algorithm have been made it a powerful tool to deal with challenging optimization problems. Almost all of the previous implantations of PSO are in the FPGA or software frameworks. Long execution time is the main reason why these works are deficient for real-time applications. Instead, CMOS is a favorable alternative from delay and area point...
In this paper, a novel readout scheme for the one-transistor one capacitor (1T-1C) DRAM will be introduced. The scheme depends on charging the bitline as well as the cell-storage capacitance to a certain level and comparing the charging current with a reference current to disclose the stored data. The factors affecting the sense margin will be discussed. The proposed readout scheme will be verified...
This paper presents an optimal design of a CMOS Low Noise Amplifier (LNA) implemented in the inductive source degeneration topology using Particle Swarm Optimization (PSO) technique. The optimized design has a substantially low noise figure with better forward gain. The proposed LNA is made to work at 2.4 GHz and is implemented in 0.18μm CMOS technology. It has a forward gain of 32 dB and a noise...
We study the logic synthesis of emerging nanotechnologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow designers to validate majority-based nanotechnologies on large-scale benchmarks. We describe models and data-structures for logic design with majority-based...
Spin Wave Devices (SWDs) are promising beyond-CMOS candidates. Unlike traditional charge-based technologies, SWDs use spin as information carrier that propagates in waves. In this scenario, the logic primitive for computation is the majority gate. The majority gate has a greater expressive power than standard NAND/NOR gates, allowing SWD circuits to be more compact than CMOS, already at the logic...
Device power characteristic changes significantly in 28nm CMOS technology. Consequently, some power reduction design methods that had been effective and successful in larger technology nodes become less effective or no longer useful in 28nm CMOS designs. This paper describes such changes in power reduction methods from production SOC design perspective.
Reconfigurable computing architectures combine the flexibility of software with the performance of custom hardware. Such architectures are of particular interest at the nanoscale as well. We argue that a bottom-up self-assembled fabric will be easier and cheaper to manufacture, however, one has to make compromises with regards to the device regularity, homogeneity, and reliability. In this paper we...
A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM...
A 12-channal 120-Gb/s optical receiver front-end amplifier array has been designed in a 0.18-μm CMOS process. This front-end amplifier array incorporates transimpedance amplifiers (TIAs) and limiting amplifiers (LAs). A regulated cascode (RGC) input structure, active inductor peaking and feedback technique are exploited to enhance the bandwidth without deterioration of the other performances. And...
Parametric yield loss has become a significant issue in the design of nanometer integrated circuits (IC). In this paper, the impact of supply (Vdd) and threshold voltage (Vth) variations on the yield loss for the current and future CMOS technologies is investigated. The results demonstrate that, despite the temporary improvement due to the use of high-k dielectric materials and metal gates (HiK+MG),...
In this paper a novel approach to optimize digital integrated circuits yield with regards to speed and area/power for aggressive scaling technologies is presented. The technique is intended to reduce the effects of intra-die variations using redundancy applied only on critical parts of the circuit. The inherent property of the technique is that the improvement in the maximum frequency the circuit...
Analysis and optimization process of single stage low power low noise amplifier (LNA) in CMOS technology has been presented. Input and output matching networks has been designed using derived analytic equations. Noise figure of LNA has been analyzed using accurate noise model for various noise contributors, including both of transistors in the cascode stage and substrate. Optimization process has...
We propose a novel design flow for mismatch and process variation aware optimization of nanoscale CMOS active pixel sensor (APS) arrays. As a case study, an 8 times 8 APS array is designed using the proposed methodology for 32 nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been measured. The baseline results show a power...
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impact the data-dependent power of deep submicron cryptosystem designs. In this paper, we use Monte Carlo methods in SPICE circuit simulations to analyze the statistical properties of the data-dependent power with predictive 45...
Summary form only given. Power reduction is becoming a critical design criterion for ASIC/SOC designers. Reducing both dynamic and leakage power is imperative to meet power budgets for portable devices as well as to ensure that the systems that these ASICs meet their packaging and cooling costs. In addition, the power of an ASIC has a significant impact on its reliability and manufacturing yield....
Recent studies show quantum-dot cellular automata (QCA) as one of the promising alternatives to CMOS technology. Optimization plays an important role in circuit design despite the used technology. One possibility is the minimization of the number of basic building blocks usually resulting in less energy consumption and fewer delays in processing. The principles of evolutionary computation have already...
With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters. In time, substantial device parameter degradation can occur, resulting...
This paper describes a novel gate-level dual-threshold total power optimization methodology (GDTPOM) principle, which is based on the static timing analysis (STA) and total power consumption optimization techniques for designing high-speed low-power SOC applications using 90 nm MTCMOS technology. Based on the GDTPOM principle, a multiplier circuit, which has been designed using 90 nm MTCMOS technology,...
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises superiority in exploring the flexibility offered by a design over all previous representation methods. In this work, we illustrate how the SPFD of a particular wire reveals information regarding the number of potential transient...
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