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In FinFET-based VLSI designs, heat issues from increase of driving current with temperature and self-heating effect profoundly influence the circuit performance and reliability. This work evaluates the performance of FinFET-based combinational circuits considering BTI stress and thermal effect of supply voltage and frequency variations. The proposed simulation framework is applied to selected benchmark...
In the era of deep-nanoscale transistors, 3D structure of a FinFET strengthens the self-heating effect (SHE) that intensifies aging degradation. However, unlike planar devices, heat in FinFETs can improve the circuit performance due to the temperature effect inversion (TEI). This work investigates the impact of bias temperature instability (BTI) on long-term circuit performance in the presence of...
FinFET technology has increasingly been adopted for use within integrated circuits thanks to its superior electrical integrity and scalability. However, most recent studies have concluded that FinFET circuits tend to be more vulnerable to negative bias temperature instability (NBTI) compared to planar MOSFET designs as a result of the self-heating effect. In this paper, we contrarily reveal that under...
A severity of hot carrier injection (HCI) in PFET becomes worse than NFET at elevated temperatures. This new observation is further found to be due to the coupled self-heating effects (SHE) during DC HCI stress (also a higher Ea in PFET HCI), rather than the negative bias temperature instability (NBTI) effect during HCI stress. Furthermore, in order to guarantee the precise estimation of HCI under...
As planar MOSFETs is approaching its physical scaling limitation, FinFET becomes one of the most promising alternative structure to keep on the industry scaling-down trend for future technology generations of 22 nm and beyond. In this paper, we propose a unified reliability model of Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) for double-gate and triple-gate FinFETs,...
This paper presents the asymmetric issue of FinFET device after hot carrier injection (HCI) effect and impact on the digital and analog circuits. The interface state distribution along the FinFET channel is first extracted from hot carrier injection experimental data, and then develops a compact FinFET model to simulate the impact on asymmetric distribution of interface states to the device characteristics...
A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.
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