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Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of...
System-on-chips (SoCs) are being widely adopted in mobile applications, and are driven by the need for longer battery life, their power budget continues to decrease. In addition, the phase-locked loop (PLL) for the SoC host clock has to be a very low power circuit to support the always-on always-connected (AOAC) feature for SoCs integrated into hand-held devices. The proposed PLL, imple mented in...
A 671G0PS/W Semantic Analysis SoC (SASoC) is implemented in 90 nm CMOS technology. Two stream processing systems are integrated with a power-aware frequency scaling technique to simultaneously accelerate video processing and machine-learning algorithms. The input data rate reaches 76.8 Gpixel/s for video processing and 51.2 Gdimension/s for machine-learning algorithms.
TTRAM can provide high speed, low power and high density with CMOS compatible SOI process. However it is difficult to handle as the unified memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efficiency, and lower voltage operation for dynamic frequency and voltage control. The enhanced TTRAM (ET2RAM) can solve these issues and the...
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