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A 60 GHz phase-locked loop (PLL) using an inductor-less divide-by-3 injection locked frequency divider is presented. The PLL employs a simple and fast calibration algorithm which adjusts the locking range of the injection locked divider by measuring its free running frequency. The PLL is fabricated in 90 nm CMOS. The measured result shows the calibration algorithm converges within 15 µsec with only...
A 4.5-GHz 256~511 multi-modulus frequency divider for frequency synthesizers is demonstrated. The proposed frequency divider is based on phase switching technique and cascade of divide-by-2/3 cells, it prevents the presence of control logic gates in the highest frequency division block in order to achieve the highest operation frequency under low power consumption; the division ratio is ranged from...
A 5V, 0.6μm CMOS phase locked loop (PLL) is presented. The circuit design of the PLL, which consists of a phase-frequency-detector (PFD), charge-pump (CPP), bias-generator (BG), voltage controlled oscillator (VCO) and differential to single converter (DSC), is introduced and the simulation results are given. The details of design theory and calculation are also described. The PLL is integrated in...
An all-digital frequency-locked loop (ADFLL) based frequency synthesizer with a built-in FSK modulator for medical implants communication systems (MICS) band applications is presented. The ADFLL uses a high resolution single-bit digital ΣΔ frequency discriminator in the feedback path and a ΣΔ phase accumulator in the reference path, achieving fractional resolution. The ADFLL uses a digital IIR-based...
Implemented fractional-N frequency synthesizer architecture based upon Pulse Width Locked Loop technique eliminates the need for ???? modulator within the loop while preserving the frequency resolution and accuracy of such synthesizers. Eliminating the modulator allows the designer to optimize the synthesizer loop bandwidth without any constraint imposed by the modulator. The loop operates by locking...
In this paper, a frequency tunable differential input differential output low noise amplifier (LNA), used for 3-5 GHz OFDM applications, is proposed and analyzed. The LNA has a wideband input matching and a tunable output matching. The digital controlled capacitor arrays in the output matching networks allow the LNA to be switched smoothly in the frequency range of 3 to 5 GHz with output return loss...
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 ??s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
There has been significant interest in the applications of printed electronics in the realization of fully-printed RFID tags and embedded sensors. Printing of active circuitry is expected to enable a dramatic reduction in the overall cost of these systems, allowing for integration of electronic barcodes and product quality detection systems into consumer goods. In this talk, I will review our work...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
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