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In this work, we propose an efficient architecture for the hardware realization of deep neural networks on reconfigurable computing platforms like FPGA. The proposed neural network architecture employs only one single physical computing layer to perform the whole computational fabric of fully-connected feedforward deep neural networks with customizable number of layers, number of neurons per layer...
The availability of intelligent embedded system to assist the classification application is a great challenge in machine learning field in last few decades. Extreme Learning Machine (ELM) is one of the best learning methods for the implementation due to its classification accuracy and speed. The main computational effort of ELM is to compute the pseudo-inverse of hidden layers output. This work presents...
In this paper, we present a Programmable SoC device with monolithically integrated RF-ADCs and RF-DACs in a 16nm FinFET process. The device includes quad ARM Cortex-53 and dual ARM Cortex-R5 processing subsystem, 750K programmable logic cells, 4000 DSP slices and 4 32Gb/s serial transceivers. Each 14-bit RF-DAC operates at a sample rate of up to 6.4GS/s and can directly synthesize RF carriers up to...
In the dataflow computation model, instructions or tasks are fired according to their data dependencies, instead of following program order, thus allowing natural parallelism exploitation. Dataflow has been used, in different flavors and abstraction levels (from processors to runtime libraries), as an interesting alternative for harnessing the potential of modern computing systems. Sucuri is a dataflow...
The security of Internet of Things (IoT) devices including consumer products has been pointed out. Therefore, authenticated encryptions, which perform both encryption and authentication, have been attracted attention. SIMON-JAMBU is a lightweight authenticated encryption and it passed the second round of CAESAR which determines the standard of authenticated encryptions. Regarding security of hardware,...
In this paper, the method of downsizing 4K uncompressed video signal generator is introduced. It is required large data transmission bandwidth to output uncompressed 4K video signal. A SSD is known as a storage device with large data transmission bandwidth. The conventional technology for producing 4K uncompressed video output was redundant arrays of inexpensive disks technology using multiple SSDs...
FPGAs are promising candidates for computational tasks in space. However, they are susceptible to radiation-induced errors in their configuration memory. The recovery of configuration errors, either by device scrubbing or by module-based recovery, involves a series of reads and writes to the FPGA's configuration port, and is efficiently performed on-chip by a fast, flexible and reliable reconfiguration...
Convolutional neural networks (CNNs) are deployed in a wide range of image recognition, scene segmentation and object detection applications. Achieving state of the art accuracy in CNNs often results in large models and complex topologies that require significant compute resources to complete in a timely manner. Binarised neural networks (BNNs) have been proposed as an optimised variant of CNNs, which...
Stencil computations represent a highly recurrent class of algorithms in various high performance computing scenarios. The Streaming Stencil Time-step (SST) architecture is a recent implementation of stencil computations on Field Programmable Gate Array (FPGA). In this paper, we propose an automated framework for SST-based architectures capable of achieving the maximum performance level for a given...
We discuss the feasibility of an in-house Schrödinger equation solver on the Intel Broadwell Xeon processor with a built-in FPGA, with a particular focus on the performance of large-scale sparse matrix-vector multiplication (SpMV) that is the core numerical operation of electronic structure simulations for multi-million atomic systems. The double-precision SpMV section in our solver is offloaded to...
Due to severe power and timing constraints of the "things" in the Internet of things (IoT), cryptography is expensive for these devices. Custom hardware provides a viable solution. However, implementations of cryptographic algorithms in the devices need to be upgraded frequently compared to the longevity of these "things". Therefore, there is a critical need for reconfigurable,...
P4 is a domain specific language designed to define the behavior of a programmable data plane. It facilitates offloading hardware-suitable Network Functions (NFs) to a data plane. Consequently, NFs can maximally benefit from high performance of hardware devices, meanwhile more CPU power can be reserved for user applications. However, since the programmable data plane provides an NF with an exclusive...
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port (ICAP) controller is an important part of reconfiguration system with which to access the configuration registers of FPGA. By reducing the resources consumed by ICAP controller, more resources will be available for the reconfigurable...
Proton induced SEU cross-sections of the SRAM which stores the logic configuration and certain functional blocks of the Zynq UltraScale+ MPSOC are presented. Upset rates in the space radiation environment are estimated.
In this work we present a FPGA-based system for real-time processing of neural signals acquired by commercial high-density microelectrode array (HDMEA). The considered MEA features 4096 electrodes with 18kHz sampling frequency and 12-bit resolution, thus produces nearly 1 Gbps of data. Within the implementation, we considered low-latency as a main objective, to allow for closed-loop acquisition-stimulation...
Physical Unclonable Function (PUF) has been attracted attention as a countermeasure of an imitation of semiconductor. Pseudo linear feedback shift register PUF (PLFSR PUF) is one of the most popular PUFs. However, a performance evaluation of PLFSR PUF due to the difference of implementation has not been reported. Therefore, this study evaluates the performance of PLFSR PUF with several implementation...
High-density microelectrode arrays (HDMEAs) are promising tools to tackle fundamental questions in neuroscience and brain diseases with unprecedented experimental capabilities. The acquisition of the biological signals sampled by such MEAs, that usually involves filtering, preliminary processing and finally data storage, is an intrinsically parallel and computation-intensive activity, particularly...
The increased use of application-specific computational devices turns even low-power chips into high-performance computers. Not only additional accelerators (e.g., GPU, DSP, or even FPGA), but also heterogeneous CPU clusters form modern computer systems. Programming these chips is however challenging, due to management overhead, data transfer delays, and a missing unification of the programming flow...
Big data and machine learning applications are posing steadily increasing challenges to the used compute platforms in terms of performance and energy efficiency. In this paper we utilize the highly scalable heterogeneous server platform RECS for evaluation of a wide variety of hardware platforms ranging from general purpose CPUs via ARM-based SoCs to GPGPUs and FPGAs. The self-organizing map, a popular...
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