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In this work, we propose an efficient architecture for the hardware realization of deep neural networks on reconfigurable computing platforms like FPGA. The proposed neural network architecture employs only one single physical computing layer to perform the whole computational fabric of fully-connected feedforward deep neural networks with customizable number of layers, number of neurons per layer...
Multilayer perceptron neural networks have widely been implemented on reconfigurable hardware to perform a variety of applications including classification and pattern recognition. This paper investigates the combined impact of neural network size and reduced precision number formats, used for the representation of the optimal parameters, on the recognition rate a neural network based handwritten...
Embedded CPUs typically use much less power than desktop or server CPUs but provide limited or no support for floating-point arithmetic. Hybrid reconfigurable CPUs combine fixed and reconfigurable computing fabrics to balance better execution performance and power consumption. We show how a Stretch S6 hybrid reconfigurable CPU (S6) can be extended to natively support double precision floating-point...
One challenging task for VLSI and reconfigurable system design is the identification of the smallest number format possible to implement a given numerical algorithm guaranteeing some final accuracy while minimising area used, execution time and power. We apply affine arithmetic, an extension to interval arithmetic, to estimate the rounding error of different floating-point dot-product variants. The...
Applications requiring double precision (DP) arithmetic executed on embedded CPUs without native DP support suffer from prohibitively low performance and power efficiency. Hybrid reconfigurable CPUs, allowing for reconfiguration of the instruction set at runtime, appear as a viable computing platform for applications requiring instructions not supported by existing fixed architectures. Our experiments...
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