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The usage of Cellular Automata (CA) for image processing tasks in self-organizing systems is a well known method, but it is a challenge to process such CAs in an embedded hardware efficiently. CAs present a helpful base for the design of both robust and fast solutions for embedded image processing hardware. Therefore, we have developed a system on a chip called ParCA which is a programmable architecture...
This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform...
Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements...
A hardware/software co-simulator has been developed for a video processing SOC. The simulator is composed of a PC and a FPGA board. The simulator realizes seamless connection between software on a PC and hardware circuits in a FPGA chip. Therefore, partial VLSI design is possible within the software. As modification on both software system and FPGA circuits are easy and as the simulation speed is...
The increasing complexity of today's system-on-a-chip (SoC) design is challenging the design engineers to evaluate the system performance and explore the design space. Electronic system-level (ESL) design methodology is of great help for attacking the challenges in recent years. In this paper, we present a system-level architecture refinement flow and implement a dual DSP cores virtual system based-on...
This paper summarizes the experiences of global faculty (N. America, Europe, Asia) in using an open design platform approach for project-based active learning in electronics, computing and ICT engineering education. A common design platform was used to support courses spanning a range of university engineering levels from 2nd year undergraduate to 2nd second year postgraduate programs, and across...
With the developing of the integrated circuit design and fabrication technology gradually, system-on-chip (SoC) technology has been widely used because of its high performance such as small size, low power consumption and so on. This paper describes a digital three-phase SPWM signal generation SoC based on OpenRISC1200, a 32-bit RISC processor core. The system integrates parameter controlling, displaying...
To deal with nowaday multi-standard audio and video processing, a heterogeneous multi-core SOC architecture is presented in this paper, which is composed of a general purpose RISC processor, an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding, an efficiency and flexible HW/SW cooperating architecture is...
A current trend in digital signal processing is to reduce power and energy consumption. The use of asynchronous designs is one of the possible ways to achieve these goals, but the nature of these circuits requires different modeling schemes. We present in this paper our own model for a novel DSP architecture comprising multiple asynchronous cores and ALUs per core. Our approach shows how to match...
Transport triggered architecture (TTA) is one kind of application-specific instruction processors (ASIP), which fits embedded systems and offers a cost-effective trade-off between the energy-efficiency and performance. However its architecture and very long instruction word (VLIW) are alike, which also results in a very poor code density. In embedded systems, memory is one of the most expensive resources...
AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform independent software package is developed for AVS1-P2 decoder to facilitate embedded video codec development. In order to minimize the on-chip memory and save the time consumed in on-chip/off-chip data...
Advances in chip technology have enabled integrating many functional units on a single chip. This led to the emergence of the concept of system-on-chip (SoC) which is used extensively in the development of advanced embedded systems. Embedded systems are widely used today in different digital signal processing (DSP) applications that usually require high computation power and tight constraints. Using...
The technological revolution during the last years has carried out a great evolution especially in the multimedia domain. Nowadays, almost everyone benefits from various video applications such as TV broadcasting and video conferencing. This progress involves particularly an increase in the capacity of digital data transmission. As a result, data compression became increasingly significant for storage...
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an on-chip processor. This gives higher flexibility compared to implementing an evolutionary algorithm directly in hardware, since the parameters and behaviour of the algorithm can easily be changed, and complex operators are more feasible...
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