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As power consumption of the cache memory in modern processor designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing instruction cache power based on the operation of a local access control scheme added in the cache system. The average saving on the power consumption of the instruction cache could be up to 23% compared with the traditional...
With the migration of a wireless sensor network (WSN) over various evolving applications, power estimation and profiling during the design cycle become critical issues and present hurdles in reducing the design time. Furthermore, with a growing size of the network, simulating the behavior of each sensor node is not feasible. It is important to devise an approach that provides a network-wide picture...
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temperature in DRAM chips. As a result, temperature management has become a real and pressing issue in high performance DRAM systems. Traditional low power techniques are not suitable for high performance DRAM systems with high...
Communication latency and power consumption are two competing objectives in network-on-chip (NoC) design. This paper proposes a novel method that unifies these two objectives in a multi-commodity flow (MCF) formulation. With an improved fully polynomial approximation algorithm, power efficient design of an 8 times 8 NoC can be found for given average latency constraints with certain communication...
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