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A voltage feedback charge-cancellation technique is proposed which prevents the conversion nonlinearity due to the parasitic effect of split DAC architecture in Successive Approximation Register (SAR) ADCs. A voltage feedback network operating as a capacitive charge-pump can efficiently detect and compensate the voltage error in each bit cycling, thus the conversion accuracy can be significantly improved...
The attenuation of supply noise is crucial in those sensor interface circuits that require the detection of the small signal capacitance. This paper presents an integrated charge-pump based continuous frequency regulator for precision supply voltage generation. The circuit is able to operate with external supply voltage ranging from 3.0 V to 5.5 V. The charge-pump generates a nominal voltage of 3...
Power autonomy is an important requirement for wireless sensor nodes. Thermoelectric generators can produce sufficient power for low power applications. Due to varying temperature, a power management circuit will be required. This paper presents such a power management circuit, realized in the AMIS I3T80 CMOS technology. It contains a Dickson charge pump with a variable number of stages as a DC/DC...
The purpose of this paper is to explore power harvesting capabilities in nanometer technology. Novel charge pump improvements using the back-gate or well of MOS devices improve efficiency as well as sensitivity. The proposed circuits are implemented in 90 nm CMOS. Measured performance will be provided.
This paper presents a theoretical study on clock control strategy of four-phase Dickson charge pump for improving the power efficiency. Optimized clock control signals attains better power efficiency when compare the conventional designs. Simulation results based on the 0.25 mum CMOS technology are presented to validate the analysis.
This paper presents a compact power efficiency model to be applied in the analysis and design of clock overlapping of four-phase Dickson charge pump. The hands in equations on the optimal clock overlapping are concluded. Based on 0.25 um CMOS technology, the proposed model is consistent with the simulation result. Both simulation and model validate the optimal clock overlapping range attains better...
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