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A problem-oriented processor on the basis FPGA for high-precision calculations in floating-point formats (64-, 80-, 128-bit) for solving poorly conditioned systems of linear algebraic equations by the Gauss method was developed.
The distribution of data retention time of DRAM cells heavily dominates the refresh power consumption and fabrication yield. Although merely extending the single standard refresh period can effectively reduce the refresh power, however, it will incur more data retention faults (DRFs). In this paper, a novel sub-bank address remapping (SBAR) technique is proposed to cure this dilemma. Memory blocks...
Energy saving management in multi-core embedded environments has been a challenge for designers. To achieve energy efficiency, most studies consider dynamic frequency scaling on one hardware component only, such as processor or memory — which will most likely also affect performance. This work proposes the use of frequency scaling considering the three most important hardware components altogether:...
With the increasing complexity of modern Systems-on-Chip, the possibility of functional errors escaping design verification is growing. Post-silicon validation targets the discovery of these errors in early hardware prototypes. Due to limited visibility and observability, dedicated design-for-debug (DFD) hardware such as trace buffers are inserted to aid post-silicon validation. In spite of its benefit,...
The motion estimation stage requires high number of memory accesses, causing high-energy consumption in the video coding process. This results in lower battery lifetime on mobile devices. Thus, solutions to reduce the external memory bandwidth in video coding systems must be used. This work proposes a memory energy consumption analyzer, which estimates the energy consumption related to memory accesses...
The common DPU platform for ESA JUICE mission instruments is a hardware and software platform developed by Cobham Gaisler for the scientific instrument payloads of the European Space Agency Jupiter Icy Moons spacecraft. The hardware is based around the GR712RC dual-core LEON3-FT processor with GRSPW2 SpaceWire interfaces. To accompany the JUICE instrument hardware, a flight quality SpaceWire software...
The Internet of Things (IoT) is projected to soon interconnect tens of billions of new devices, in large part also connected to the Internet. IoT devices include both high-end devices which can use traditional go-to operating systems (OSs) such as Linux, and low-end devices which cannot, due to stringent resource constraints, e.g., very limited memory, computational power, and power supply. However,...
The paper discusses the design process of a full programmable logic controller implemented by means of FPGA device. The PLC is compliant with EN 61131-3 standard. It is equipped with a programmer that allows to transfer a program to the program memory of the controller, and the I/O controller which allows the exchange of information with the outside world, i.e. the signal modules. Some interesting...
This paper describes the implementation of a system for measuring entropy. The design was optimized to be implemented in a simple and small microcontroller, achieving acceptable accuracy. The system allows measuring the entropy of internally code-generated signals, and also, sampled external analog signals. The development board used M1AFS-embedded kit of Actel. In the FPGA (Field Programmable Gate...
Los Alamos National Laboratory has designed and manufactured a single-board computer (SBC) for deployment in space-flight applications. The SBC is designed to meet the command- and data-handling requirements for missions requiring true space-grade radiation hardness and fault tolerance, exceeding those that are typical in CubeSat and SmallSat applications but at a substantially lower cost, lower power,...
The increasing adoption of GPUs as mainstream computing devices, coupled with the imminent availability of large high-bandwidth caches based on die-stacked memory makes it important to analyze and understand modern GPU compute applications from the perspective of their memory access and data reuse characteristics. This paper presents detailed workload characterization studies on four GPU compute applications...
6LoWPAN (IPv6 over Low Power Wireless Personal Area Networks) is gaining more and more attraction for the seamless connectivity of embedded devices for the Internet of Things. It can be observed that most of the available solutions are following an open source approach, which significantly leads to a fast development of technologies and of markets. Although the currently available implementations...
The Hybrid Memory Cube (HMC) is a promising alternative to DDRx memory due to its potential to achieve significantly higher bandwidth. However, the high static power of an HMC device compromises power efficiency when the device is lightly utilized. Activating a sleeping HMC takes over 2µs, which makes it challenging to manage HMC power without a substantial degradation in system performance. We introduce...
This work presents the framework Cloud Testing, a solution to parallelize the execution of a test suite over a distributed cloud infrastructure. The use of a cloud as runtime environment for automated software testing provides a more efficient and effective solution when compared to traditional methods regarding the exploration of diversity and heterogeneity for testing coverage. The objective of...
This paper describes efficient hardware architecture for the deblocking filter used in H.264/AVC baseline profile video coding standard. The deblocking filter is a computationally and data intensive tool leading to an increased execution time of both encoding and decoding processes. In fact, we propose a novel edge filter ordering which needs 64 clock cycles to filter a Macroblock (MB). A specified...
This paper proposes and studies an hibernation technique and optimal hibernation policies aimed at minimizing the power consumption, while allowing stateful processing and the adoption of more powerful nodes. To this purpose the paper models the energy trade-off for hibernating the system rather than putting it in a memory-retention sleep mode between two consecutive bursts of processing. Thanks to...
Classification systems specifically designed to deal with fully labeled graphs are gaining importance in many application fields. The main computational bottleneck in such systems is the dissimilarity measure between pairs of graphs. In this paper we propose to accelerate in hardware such computations, relying on the Graph Coverage as the core inexact graph matching procedure, targeting the design...
4 or 8-point IDCT are widely used in traditional video coding standards. However larger size (16/32-point) IDCT has been proposed in the next generation video standard such as HEVC. To fulfill this requirement, this work proposes a fast computational algorithm of large size integer IDCT. A unified VLSI architecture for 4/8/16/32-point integer IDCT is also proposed accordingly. It can support the following...
Aiming at the mixed use of fieldbus in industry automatic controlling system, the paper proposes a method of multi-functional gateway based on singlechip in order to reach an inter-coordination and compatibility among different protocol standards of fieldbus. Using singlechip as the core of the system ,a proposal of inter-communication among the standard bus interfaces of CAN(Controller Area Network),...
Advanced Encryption Standard (AES), a Federal Information Processing Standard (FIPS), is an approved cryptographic algorithm that can be used to protect electronic data. The AES can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker and more customizable solution. This paper presents the AES algorithm with regard to FPGA and the Very...
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