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This paper presents a high-bandwidth 2 GHz CMOS variable gain amplifier (VGA) for using in the band of square kilometer array (SKA) range that achieves an 18 dB dynamic range (DR) while powered from a single 1.8 V supply. This VGA capability is obtained by employing a passive digital T-bridge attenuator followed by a fixed amplifier, the use of attenuator in the front end of the VGA results in a high...
This paper reviews efficient amplification techniques, such as a load modulation, an envelope tracking (ET), an envelope elimination and restoration (EER), an outphasing and a digital modulation for signals with high peak-to-average power ratio (PAPR). Implementations of these techniques in the state-of-art CMOS power amplifiers are compared.
The demand for higher data rated has lead to the utilization of both higher frequency bands, where power amplifiers (Pas) are inherently less linear, as well as carrier aggregation (CA) where linearity requirements are more stringent. In addition, cost reducing tactics for large volume applications naturally lead to CMOS based PAs which are less linear than the commonly used GaAs PAs. Envelope tracking...
A fully-integrated differential cascode linear CMOS power amplifier (PA) with adaptive gate bias circuits is reported. The active bias circuits are employed to achieve a high linearity from a deep class-AB biased common-source stage. The gate bias of the common-gate stage is adapted to linearize the severe distortion of the deep biased amplifier at a low power region. An envelope signal is injected...
Among the significant remaining challenges of complete transceiver integration for handset applications is the implementation of high-efficiency power amplifiers (PA) in CMOS. This challenge is exacerbated by the high crest factors of the signals utilized in WCDMA and LTE standards. The first aim of this paper is to identify the shortcomings of the traditional efficiency enhancement techniques in...
Modern communication networks demand power amplifiers (PAs) which are efficient and have low distortion. The common drain amplifier has the potential to become a linear amplifier with good efficiency, when biased at or above class-B. The main challenge is to provide unconditional stability while still maintaining adequate transducer gain so that the power added efficiency (PAE) will not be compromised...
A 20-29 GHz wideband CMOS low-noise amplifier (LNA) with flat and low noise figure (NF), flat and high gain (S21), and excellent phase linearity property (group-delay-variation is only ±22.6 ps across the whole band) is demonstrated. To achieve flat and low NF, the size, layout and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was...
A highly efficient CMOS linear power amplifier for WCDMA applications with feedback bias technique is presented. The method involves connecting the gates of common-gate devices of the driver stage and the power stage in cascode configurations by a feedback network for enhancing linearity. To achieve high efficiency and linearity simultaneously, large-signal IMD minimum (IMD sweet spot) is properly...
A 53.5-62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of -10.3~ -19.5 dB, output return loss (S22) of -13.8~ -27.8 dB, forward gain (S21) of 8.1~ 11.1 dB, and reverse isolation (S12) of -49.9~ -60.2 dB over the...
A direct down conversion Gilbert-type mixer in combination with an active low-pass filter for 4MHz is presented. The Gilbert-type mixer is enhanced with a source degeneration to improve the linearity performance. The active filter is a linearity enhanced differential amplifier with feedback network. For the high supply voltage of 2.5V additional over-voltage protection with cascodes is added to the...
Ultra wideband (UWB) low-noise amplifiers (LNA) are one of the key features in modern radiofrequency and microwave receivers. This paper presents an enhanced 3-7 GHz common-source LNA in 130 nm CMOS technology. Coupled to an inverse Tchebycheff band-pass filter, the proposed system led to a high gain while reducing the noise distribution and improving the amplifier linearity. Indeed, with a power...
A continuous-time low pass filter (LPF) for high bandwidth application is presented in this paper. The LPF is realized with 6th order Chebyshev structure. Large dynamic range is achieved by adopting linearity enhanced technique. A 6-bit controlled switched-capacitor array is realized to get wide programmable cut-off frequency. The measurement results indicate that the -3 dB cut-off frequency can be...
A high-performance 13 bit current-steering DAC for analog subsystems is implemented in a standard 0.13 mum CMOS technology. A novel dynamic background calibration scheme directly trims the unary DAC-elements in differently weighted segments of the current source array. Interleaved current cells implement an effective RZ- behavior with NRZ output current waveform, which improves the dynamic linearity...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A low power 6-bit ADC that uses reference voltage and common-mode calibration to improve linearity and reduce power dissipation is presented. The ADC occupies 0.13 mm2 in 65 nm CMOS. The ADC dissipates 4 mW at 100 MS/s and 12 mW at 800 MS/s from a 1.2 V supply.
An RF power MOSFET was proposed and manufactured in a standard 0.13 μm CMOS technology. Without adding additional masks, cost and process, the breakdown voltage can be improved by using the N-well and shallow-trench-isolation processes to form a drift n- region. The breakdown voltage was 4.3 V at gate bias of 1.2 V. The cutoff frequency and maximum oscillation frequency were 68 GHz and 87 GHz, respectively...
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