The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An original and modern integrated current sensor is designed and presented in this paper. It can provide a sense current proportional to an output current available to the microcontroller via an external resistor. The ratio between output and sense current is modeled and simulated. The errors between the two currents increase in low currents domain. A solution consisting in a gate back regulation...
The fully differential class-AB OTA topology by Peluso presents a poor Common-Mode Rejection Ratio (CMRR) and could become unusable for a common-mode gain larger than 1. We propose a local feedback loop that exploits internal nodes and triode-biased transistors to improve the CMRR with a limited power and area penalty. Simulations in 40-nm CMOS technology show a net improvement of the CMRR without...
In this paper, different topologies of gate-driven and bulk-driven current mirrors designed in 90 nm CMOS technology are presented. Since the conventional MOS transistors can work as a bulk-driven device, there is no need for any modification of the existing MOSFET structure or technology process. The bulk-driven current mirror is capable of operating at power supplies down to the threshold voltage...
In this paper continuous time high-performance current mirrors (CMs) based on series and parallel connected unity sized CMOS transistors suitable for low power applications are presented. It is shown that the proposed implementation techniques allow an increased output resistance, from twice the output resistance of the simple current mirror (SCM) up to more than 50 times of the cascode current mirror's...
Wide-bandgap power switches, based on SiC and GaN, are emerging on the semiconductor market. Standard resistor drivers are insufficient to exploit all the advantages of these new devices. Fine control over current and voltage waveforms during switching, equivalent on-state resistance and immunity to noisy environments, demand the development of dedicated drivers. This study aims at determining a suitable...
EPC eGaN transistors have demonstrated performance improvements in comparison with Si MOSFETs ([1], [2] and [3]) but their gate is sensitive to overvoltage (recommended gate source voltage is 5V and the maximum is 6V). In this paper, an efficient insulated and fast gate driver topology is investigated considering parasitic elements. Then, a theoretical and experimental comparison is made. An IC is...
The conventional totem-pole BJT used in IGBT gate driving circuit limit the maximum output current due to desaturation of BJT's collector-to-base voltage. This paper presente a novel circuit topology to increase the output current of totem-pole BJT and also decrease the BJT power loss. As a result, the switching speed of IGBT can be raised and the switching loss of IGBT is reduced. At last, both the...
In this paper, the design of a class E synchronous rectifier, working in the 900 MHz frequency band and based on an Enhancement-mode Pseudomorphic High Electron Mobility Transistor (E-PHEMT), is proposed. Thanks to its small on-state resistance and its slightly positive threshold voltage, this type of device may offer an excellent performance when operated as a switch without biasing its gate terminal...
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
This paper demonstrates single-stage boost rectification for electromagnetic energy harvesters down to approximately 100 μW using practical low-power techniques. The circuits exploit the inductance of the generator, and operate without a discrete inductor, which facilitates integration. Experimental results demonstrate the importance of switching device selection, and the compound effect of the duty...
This paper presents a supply concept for a two channel low side switch. The circuit is supplied from the input pins, each input supplying the corresponding channel. The topology presented in this paper selects the highest input voltage to supply common blocks. Simulations are used to observe the behavior of the switch.
Magnetic feedback from a differential pair to the core of a cross-coupled oscillator reduces the effect of device losses, raising the oscillation frequency. Three prototypes using one-turn nested inductors and including on-chip downconversion mixers operate at 205 GHz, 240 GHz, and 300 GHz while drawing a power of 3.5 mW.
This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultra-low power power-scalable analog and digital integrated circuits. The proposed technique is based on using subthreshold source-coupled or current-mode approach for both analog and digital circuits. In addition to possibility of operating...
In this paper by utilizing a new concept for designing logic gates based on MOBILE, we have presented new three-input XOR and XNOR gates which were based on generalized threshold gate (GTG) topology. The proposed gates use fewer elements count in comparison with other implementations which utilize MOBILE as a main part. The correct operation of XOR and XNOR gates were confirmed by using HSPICE simulator.
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
Sublinear signal propagation delay in VLSI circuits carries a far greater penalty in wire area than is commonly realized. Therefore, the global complexity of VLSI circuits is more layout dependent than previously thought. This effect will be truly pronounced in the emerging wafer scale integration technology. We establish lower bounds on the trade-off between sublinear signalling speed and layout...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.