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This paper proposes a topology optimization method for dual-threshold (DT) independent-gate (IG) FinFET circuits. In the proposed method, a node extraction algorithm is developed to extract the characteristic nodes of a BDD expression, which are suitable to be realized with the compact logic gates based on the DT IG FinFET devices, and then the equivalent replacement program that these extracted characteristic...
An improved readout circuit interface for ion-sensitive field-effect transistor (ISFET) is proposed in this work. When compared with conventional topologies found on the literature, the proposed ISFET readout circuit presents at least two advantages. The first concerns the simplicity of the new circuity topology, and the second is the additional gain conferred to the sensor output signal. The performance...
This paper introduces a topology to combine multiple low voltage Piezoelectric Energy Harvesters with the goal of widening its harvestable frequency range and improving the power output. The architecture uses a shared inductor scheme and a rectifier-free approach. The proposed harvester is able to handle multiple harvesters efficiently by harvesting the peak energy from each harvester. The proposed...
Different low-voltage and low-power techniques, which meets modern integrated circuit design requirements, appears as the key towards achievement of enhanced performance of designed circuits. For deep sub-micron technologies, choosing a suitable transistor model becomes very important. Conventional MOS transistor models, such as BSIM or PSP, are developed for conventional gate-driven applications...
The Self Turn-ON of IGBTs leads to an increased turn-on speed. As far as IGBTs with different threshold voltages are paralleled, collector current imbalances, during turn-on, may occur. The intensity of imbalance depends on the used gate-drive topology, influenced by the Self Turn-ON.
Field effect transistor (FET) or bipolar junction transistor (BJT) based circuits, involving emitter/source degeneration by any general impedance are widely known for their positive effects on circuit performance. The circuit's behavior like input-output impedances, trans-admittance, voltage and power gains of such topologies are well known. In this paper, we propose to analyze the topology by looking...
Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance integrated circuits often use adders to achieve...
Interest in asynchronous circuits has increased in the VLSI research community due to the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. Albeit a wide variety of techniques for designing asynchronous circuits are available, quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and...
GaN-HEMT and scaling technique is analyzed. The concept of unit cell is employed to demonstrate the model. The parameters for the intrinsic and extrinsic parts of the transistor have been extracted for GaN-HEMTs and the correct topology derived such that simple scaling rules apply to the unit cell. This linear model is applied to build different peripheral devices by varying the number of gate fingers...
Analysis of several impedance matching networks used in both common source and common gate amplifiers with reactive feedback are presented. Five fundamental topologies for transformer feedback based closed-loop amplifiers are identified and their relative merits with respect to silicon area and power consumption are discussed. In addition, a design methodology to achieve both narrow and wideband matching...
A HEMT model is proposed that correctly isolates the access metallization from the intrinsic device to give linear scalability. The model uses a distributed network of intrinsic unit cells composed of lumped elements. The topology of these networks is determined such that a scalable set of parameters is obtained. The parameters for the intrinsic and extrinsic parts of the transistor have been extracted...
This paper presents an overview of research on a novel AC drive with fully integrated matrix converter that implements bus bars and active gate driving technique for overvoltage minimization during power switch commutation. This overview includes main features of power IGBT gate driving, principles of bus-bars, as well as active gate driver for power IGBT overvoltage protection.
Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes...
In this paper, we propose two new N-way arbiter circuits. One circuit is based on the token-ring arbiters and another circuit is based on the mesh arbiters. The idea of the ring arbiter is to generate a lock signal by a token which is based on the non-return-to-zero signaling. It can achieve low latency and high throughput arbitration for a heavy work load environment. The idea of the mesh arbiter...
In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation...
This paper presents an alternative topology for realizing a four-quadrant amplifier with single-ended output. In the proposed multiplier, constituting differential circuits are vertically arranged resulting in single-ended current output with output DC voltage equal to a half of supply voltage. Since the circuit operates in a current-reused mode, the power consumption is systematically reduced by...
In this paper, two topologies are proposed to develop a new self-controlled and self-protected integrated power switch. Their operation mode is analyzed using 2D physical simulation and compared.
This paper presents a general weak nonlinearity model that can be used to model, analyze and describe the distortion behavior of various low noise amplifier topologies in both narrowband and wideband applications. Represented by compact closed-form expressions our model can be easily utilized by both circuit designers and LNA design automation algorithms. Simulations for three LNA topologies at different...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
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