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This paper concerns the design and the implementation of a transimpedance amplifier (TIA) dedicated to detector of Near Infrared spectroscopy (NIRS). To reduce the effect of the input capacitance on the bandwidth, a bias circuit with low input impedance is connected to input stage. A single ended common source common gate input stage based on a cascode structure is used to get a higher gain bandwidth...
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained...
In this paper, a simple topology to reduce delay variations in domino logic gates is discussed. According to a previous analysis by the same authors, the feedback loop implemented by the keeper transistor and the output inverter gate is responsible for a delay variability increase, compared to static CMOS logic. The proposed strategy reduces the loop gain associated with this feedback loop, and hence...
A comprehensive study of dual-gate organic thin-film transistors targeting more robust organic circuitry is performed. The difference between zero-Vgs-load and diode-load logic is studied and an optimized design for both is presented. This new design is used in 99-stage ring oscillators, to determine stage delays, and in 64 b RFID transponder chips yielding data rates of 4.3 kb/s.
In this paper, a low power, area efficient Low Noise Amplifier (LNA) targeting at the lower band of the Ultra Wideband spectrum is presented in 0.13um CMOS process. The LNA uses a feedback technique based on a source follower and current bleeding, aiming to provide adequate current at the amplifying transistor without causing large voltage drop across the load resistance. A novel approach combining...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
As semiconductor technology moves closer to the ultimate physical limits for scaling of devices that utilize electrons as information bearing particles, many new opportunities for research in the physical sciences are emerging. If we look beyond the limits of scaling electron devices, many more challenging research opportunities exist in the areas of physics of information carriers and physics of...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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