The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
It is well-known that the miniaturization or scaling down process of integrated circuits (ICs) has lead to the reliability issues such as Hot-Carrier (HC) and Negative Bias Temperature Instability (NBTI) effects which are very significant on p-type MOSFET. A negative voltage is applied to the gate of a pMOSFET and it attracts more holes towards the Si/SiO2 interface. Thus the inversion holes weaken...
This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance. However, the direct implementation of the SACOX on the deep trenched MOSFET having less than 0.5 um trench...
The review addresses the major challenges that Nanoelectronics will have to face in the next decades. A multifaced strategy is followed to scale down CMOS based technology with new materials and disruptive architectures, heterogeneous integration, alternatives to MOSFET for information processing introducing 3D schemes at the Front End and back end levels.
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
Steep channel impurity-profiles formed by Si:C+Si epitaxial growth have been extensively studied. Especially in pMOS, several concerns are solved by boron-doping underneath Si:C layers. Finally, performance improvement realized by steep channel profiles has been demonstrated in both nMOS and pMOS with the same epitaxial channel structure.
In this paper, the reliability of the fluorinated hafnium oxide (HfO2) gate dielectric using novel and CMOS compatible fluorinated silicate glass (FSG) process has been studied comprehensively for the first time. Due to dangling bonds and oxygen vacancies recovery by the fluorine atoms, higher transconductance, smaller stress-induced threshold voltage and interface state degradation are therefore...
For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down...
We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
We report, for the first time, a simple and cost effective co-integration of strained p and n-FETs using tin (Sn) and mono-carbon (C) implant in Source/Drain (S/D) of p- and n-FETs, respectively, to induce beneficial strain. For the first time, a single laser anneal step was employed to substitutionally incorporate the Sn and C atoms simultaneously into lattice sites. 7 at.% substitutional Sn concentration...
State-of-the-art low-K spacer technology featuring novel CVD-SiBCN material is demonstrated for the first time. A significant 20% CMOS ring speed enhancement is demonstrated with SiBCN (K=5.2) spacer, compared to Si3N4 (K=7.5) spacer, due to reduced fringing capacitance and enhanced strain effects by spacer-PSS and CESL techniques. Electron mobility is improved by 6% for long channel NMOS transistor...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.