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In this paper a random number generation method based on a piecewise linear one dimensional (PL1D) discrete time chaotic maps is proposed for applications in cryptography and steganography. Appropriate parameters are determined by examining the distribution of underlying chaotic signal and random number generator (RNG) is numerically verified by four fundamental statistical test of FIPS 140-2. Proposed...
Power leakage through side-channels has been utilized by attackers to recover secret information in embedded cryptographic systems, and various countermeasures have been devised to mitigate this kind of leakage. In hardware systems, examples of such countermeasures include power balance circuits and masked gates. Power balance technologies such as Wave Dynamic Differential Logic (WDDL) aim to balance...
Side-channel attacks have been a serious threat to the security of embedded cryptographic systems, and various countermeasures have been devised to mitigate the leakages. Power balance technologies such as wave dynamic differential logic (WDDL) aim to balance the power by introducing differential logic. However, different routing length leads to different capacitance of wire, and this hampers the...
The goal of t-private circuits is to protect information processed by the circuit. This work presents the first practical power analysis evaluation of t-private logic style for FPGAs. Following the synthesis technique introduced at HOST 2012, a t-private S-box of the Present block cipher is synthesized and analyzed with respect to side channel leakage. The analysis is performed on simulated power...
An RTL countermeasure intended to protect the AddRoundKey and SubByte steps of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on first order CPA attacks confirmed the effectiveness of the proposed countermeasure, especially in protecting the SBOX output, showing that even with the acquisition...
A novel RTL countermeasure intended to protect the AddRoundKey step of the AES algorithm against DPA or CPA attacks has been proposed and tested on an AES encoding coprocessor implemented on FPGA. Experimental results based on CPA attacks confirmed the effectiveness of the proposed countermeasure, showing that with 100000 acquired power curves, the absolute value of correlation function is one order...
In this paper, authors propose a new Second Order Differential Power Analysis (SO-DPA) countermeasure for AES cipher. While published results for SO-DPA are proposing multiple masking solutions and the design of two independent True Random Number Generator (TRNG), the proposed design in this paper uses only one TRNG and combines a simple masking solution with the Correlated Power Noise generator (CPNG)...
Correlation power analysis is the well-known attack against cryptographic modules. An attacker exploits the correlation between the power consumed by a device and the data being processed. In the present paper, we present the experimental procedure of correlation power analysis using three different devices: FPGA, ASIC and a microcontroller. Results show that the power model used to calculate hypothetical...
We present concepts and implementations to transform write collisions in memory blocks into an entropy source for random number generation. Write collisions in dual-ported block memories occur when both memory ports write simultaneously different data at the same memory location. After a thorough analysis of this effect, we present a robust methodology to generate digitized noise and randomness from...
Cryptographic systems are being compromised by power analysis attacks. In this paper, a novel countermeasure technique against power analysis attacks is proposed which dynamically varies the clock when executing operations (making it difficult to correlate power traces in the time domain) and inserts dummy operations during idling clock cycles (reducing the signal-to-noise ratio of the useful information)...
Side channel and fault injection attacks are a major threat to cryptographic applications of embedded systems. Best performances for these attacks are achieved by focusing sensors or injectors on the sensible parts of the application, by means of dedicated methods to localise them. Few methods have been proposed in the past, and all of them pinpoint the cryptoprocessor. However, when the cryptographic...
Security at low cost is an important factor for cryptographic hardware implementations. Unfortunately, the security of cryptographic implementations is threatened by Side Channel Analysis (SCA). SCA attempts to discover the secret key of a device by exploiting implementation characteristics and bypassing the algorithm's mathematical security. Differential Power Analysis (DPA) is a type of SCA, which...
In this paper, an automatic general-purpose Differential Power Analysis (DPA) System for cryptographic devices is designed and implemented. This system aims at testing the security of cryptographic devices, e.g., Smart Card, FPGA and ASIC circuit against DPA attacks. To verify the effectiveness of the system, a DPA attack was successfully carried out by it on an AES cryptographic ASIC chip which had...
With the large scale application of integrated circuit in the chaotic encryption, the design of cryptogram program based on the chaotic system becomes a new trend of cryptography. The digital degradation after the chaotic digitization is a key issue to be resolved, while current study pays more attention to digital chaotic period behavior, but the other characteristics of digital chaotic also plays...
A new class of physical attacks against cryptographic modules, which is called the side-channel attack, is now drawing much attention. Side-channel attacks exploit information leakage from a physical implementation, such as power consumption and electro-magnetic (EM) radiation. This paper presents an overview of the recent trends in side-channel attacks, including EM analysis attacks, and related...
There is an increasing demand for fully digital, high speed Random Number Generators because of their speed compatibility and uncomplicated integration to digital platforms. To the best of our knowledge, this paper presents the first ASIC implementation of Random Number Generator based on ring oscillators. Prototypes have been designed and fabricated by using HHNEC's 0.25 /xm eFlash process with a...
In this paper, novel circuit techniques are proposed to enhance the resistance of precharged busses against Power Analysis attacks. Indeed, a low-power low-area bus coding scheme is used to make power consumption nominally constant. In addition, a simple scrambling technique is developed in order to make the bus robust against attacks even in the presence of process variations or load unbalance. The...
The security of cryptographic implementations relies not only on the algorithm quality but also on the countermeasures to thwart attacks aiming at disclosing the secrecy. These attacks can take advantage of leakages of the secret appearing through the power consumption or the electromagnetic radiations also called ??Side Channels??. This is for instance the case of the Differential Power Analysis...
The secret key stored in a cryptographic device can be revealed from the power consumption using statistical analysis in a technique known as differential power analysis (DPA). However, DPA attacks are sensitive to measurement misalignments in the power samples that reduce the dependency between the power and the data. A countermeasure technique that increases this misalignment by inserting random...
In a high performance network security co-processor, the low power masking technique is used to promote the power attack resistant level of the AES crypto engine. Based on the original AES module which shares one S-box when ciphering and decoding, in order to achieve higher security, the novel circuit design of masking is achieved by two ways respectively, one utilized SRAM, the other replicated some...
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