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The architecture of the Microsoft Catapult II cloud places the accelerator (FPGA) as a bump-in-the-wire on the way to the network and thus promises a dramatic reduction in latency as layers of hardware and software are avoided. We demonstrate this capability with an implementation of the 3D FFT. Next we examine phased application elasticity, i.e., the use of a reduced set of nodes for some phases...
In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
Pulse compression is an important signal processing technique in radar system. Based on field programmable gate array (FPGA), an improved method for implementing pulse compression is proposed to reduce the resource usage. As the FFT and IFFT transform are the main calculations of the pulse compression and take up many resources, single FFT IP core is used to realize two operations in the improved...
In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers,...
Multi-field Packet classification is the main function in high-performance routers. The current router design goal of achieving a throughput higher than 40 Gbps and supporting large rule sets simultaneously is difficult to be fulfilled by software approaches. In this paper, a set pruning trie based pipelined architecture called Set Pruning Multi-Bit Trie (SPMT) is proposed for multi-field packet classification...
Power consumption in data centres is a growing issue as the cost of the power for computation and cooling has become dominant. An emerging challenge is the development of ldquoenvironmentally friendlyrdquo systems. In this paper we present a novel application of FPGAs for the acceleration of information retrieval algorithms, specifically, filtering streams/collections of documents against topic profiles...
A radio frequency universal smart card (RF-UCard) is a novel smart card which can support multiple chip operating systems (COS) on a single card and can enable radio frequency communication with readers. We are inspired from the traditional conference processes, and present the conference-based isolation model (CIM), a hardware architecture support for providing strong security isolation between multiple...
A cognitive radio is the final point of software-defined radio platform evolution : a fully reconfigurable radio that changes its communication modules depending on network and/or user demands. His definition on reconfigurability is very broad and we only focus on the heterogeneous reconfigurable hardware platform for cognitive radio. software defined radio (SDR) basically refers to a set of techniques...
Embedded web servers have a growing presence in a wide range of fields related to consumer electronics and industrial applications. FPGAs are a valid alternative in the implementation of these systems adding additional advantages to the traditional architectures based on microprocessors or microcontrollers. In this paper we introduce two web server implementations on FPGA devices. The first uses an...
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