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Power consumption is dramatically increasing for Static Random Access Memory Field Programmable Gate Arrays (SRAM-FPGAs), therefore lower power FPGA circuitry and new CAD tools are needed. Clock-gating methodologies have been applied in low power FPGA designs with only minor success in reducing the total average power consumption. In this paper, we developed a new structural clock-gating technique...
This paper provides the design of stream ciphers based on hash functions and an alternating step generator based on clock control. The keystream generators used for the design of stream ciphers uses low hardware and low power based circuits called Linear Feedback Shift Register circuits. The first two stream ciphers use toeplitz hash, CRC hash and keystream generation circuits whereas the third one...
A generalized power efficient clock distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed for any integer decimation factor. The Spartan3 low power FPGAs family is used to implement both proposed and conventional comb filters. From the implementation results it is shown that, applying the proposed...
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Two major gate level techniques are introduced in order to reduce the power consumption, namely the pipeline technique (with some variants) and the use of embedded RAM blocks instead of general purpose logic elements. Power...
Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too much power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process. If we can implement the techniques for power reduction in front end process then we can easily design the low power...
In multi-rate digital receivers, analog to digital converter (ADC) mostly works at a fixed sampling rate. Subsequently, a sample rate conversion (SRC) process should be executed after the ADC to extract the desired baud rate. A polyphase decomposition comb filter is widely used as a first decimation stage in SRC circuit. In this paper, a power efficient clock/data distribution technique for the input...
Motion estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex...
This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction...
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