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We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine offers cycle-accurate as well as periodic synchronization; while preserving functional accuracy, this permits tradeoffs between perfect timing accuracy and high speed with very good accuracy. When run on 6 separate physical...
Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links...
To establish a highly-efficient analytical performance model of routers is crucial for the design of NoC. In this paper, an analytical router performance model which is based on M/D/1/B queuing theory is proposed to analyze various packet blockings at the input buffers during the transfer process, and then a computing method based on Markov chain for flow-control feedback probability is presented...
In a Multi-Processor System-on-Chip (MPSoC)-based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components...
So far, many analytical models have been proposed in the literature to evaluate the performance of networks with different topologies such as hypercube,torus, mesh, hypermesh, Cartesian product networks, star graph, and k-ary n-cube; however, to the best of our knowledge, no mathematical model has been presented for irregular networks. Therefore, as an effort to fill this gap, this paper presents...
Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we present the precise formulations for the inherent reliability of mesh-based NoCs that also depend on the employed routing algorithm and traffic model. Based on this analysis, the effects of some permanent failures in the links, switches...
In recent decades, researchers try to construct high performance interconnection networks with emphasis on fault tolerance. Their studies are based on this fact that, a network can be a major performance bottleneck in parallel processors. This paper proposes an analytical model to predict message latency in wormhole-switched mesh as an instance of a fault tolerant routing. The mesh topology has desirable...
In this paper the modeling of Omega Networks supporting multi-class routing traffic is presented and their performance is analyzed. We compare the performance of multi-class priority mechanism against the single priority one, by gathering metrics for the two most important network performance factors, namely packet throughput and delay under uniform traffic conditions and various offered loads, using...
Future system-on-chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the intellectual properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For...
In order to improve scalability and reduce maintenance overhead for structured peer-to-peer systems, researchers design optimal architectures with constant degree and logarithmical diameter. The expected topologies, however, require the number of peers to be some given values determined by the average degree and the diameter. Hence, existing designs fail to address the issue due to the fact that (1)...
A routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at the same time. New router architecture is developed to support the routing algorithm. Analytical models based on queuing theory are developed for DyXY routing for a two-dimensional mesh NoC architecture, and analytical results match very well...
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