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Energy minimization is of great importance in wireless sensor networks in extending the battery lifetime. One of the key activities of nodes in a WSN is communication and the routing of their data to a centralized base-station or sink. Routing using the shortest path to the sink is not the best solution since it will cause nodes along this path to fail prematurely. We propose a cross-layer energy...
In order to improve the negative effect of increasing transformation cost of pseudo-Boolean Satisfiability algorithm in the routing process, a new routing algorithm was proposed for FPGA, which combined advantages of pseudo-Boolean Satisfiability and geometric routing algorithm. In the routing process, one of geometric routing algorithm-PathFinder was chosen firstly for FPGA routing. If not successful,...
The Network-on-Chip has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. Its importance and effect on the performance of the network is accordingly cardinal. High-performance, load-balance, deadlock-free and livelock-free, fault-tolerant are the desirable properties of a routing algorithm for NoC. In this...
In analog and mixed signal designs, exact matching requirement is critical for correct functionality of analog devices. However, due to the excessive complexity, it is difficult to consider exact matching constraint in detailed routing stage. This paper presents a novel gridless detailed routing algorithm, which efficiently obtains the optimized detailed routing solutions for a given set of nets with...
In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. Stacked mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To cope with this, an inter-layer communication mechanism is developed to enhance the buffer utilization,...
The 3D IC is an emerging technology. The primary emphasis on 3D-IC routing is the interface issues across dies. To handle the interface issue of connections, the inter-die routing, which uses micro bumps and two single-layer RDLs (Re-Distribution Layers) to achieve the connection between adjacent dies, is adopted. In this paper, we present an inter-die routing algorithm for 3D ICs with a pre-defined...
The aggressive advent in VLSI manufacturing technology has made dramatic impacts on the dependability of devices and interconnects. In the modern manycore system, mesh based Networks-on-Chip (NoC) is widely adopted as on chip communication infrastructure. It is critical to provide an effective fault tolerance scheme on mesh based NoC. A faulty router or broken link isolates a well functional processing...
To successfully route a design, one essential requirement is to allocate sufficient routing resources. In this paper, we show that allocating routing resources based on horizontal and vertical (H/V) cut-demands can greatly improve routability especially for designs with thin areas. We then derive methods to predict the maximum H/V cut-demands and propose two cut-demand based approaches, one is to...
In this paper, we introduce and study the Rectangle Escape Problem (REP), which is motivated by PCB bus escape routing. Given a rectangular region R and a set S of rectangles within R, the REP is to choose a direction for each rectangle to escape to the boundary of R, such that the resultant maximum density over R is minimized. We prove that the REP is NP-Complete, and show that it can be formulated...
Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, the Deep submicron technology foreshadows highly defective chips era. In this context, not only fault-tolerant designs become compulsory, but their performance under failures gains importance. In this paper, we present a deadlock-free fault-tolerant adaptive routing algorithm...
As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that...
The performance of Network-on-Chip (NoC) largely depends on the underlying routing techniques. In this paper we present and evaluate a fault and congestion aware routing scheme called FADyAD which combines the advantages of both deterministic and adaptive routing schemes. On the other hand, the routers switching between deterministic and adaptive routing based on the network's congestion conditions...
Boolean satisfiability based detailed routing is becoming very popular nowadays because of its capability to evaluate all the nets simultaneously. In this approach the geometric FPGA detailed routing problem can be transformed into a single Boolean function. Any satisfying assignment of input Boolean variables in the function denotes that routing is possible. Impossible routing is proved by the absence...
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding,...
In this paper, we design a topology-agnostic adaptive routing algorithm for application-specific in routing table based NoC routers. The basic idea relies on using SCC(Strongly Connected Component) based methodology, which can be done in polynomial time, to guarantee deadlock free and using mean packets arrival rate on the paths to solve the problem of paths diversity. The efficiency of the proposed...
In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links,...
The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second-level mesh. Simulation results...
Given a set of n IO buffers and a set of n bump balls on a re-distribution routing layer, an O(n(logn)2) routability-driven partition-based IO assignment is proposed to assign n IO connections for RDL routing in a flip-chip design. Firstly, based on the recursive partition of bump balls and IO buffers, the partition-based IO assignment can be obtained by using the geometrical mapping between bump...
This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about...
Irregular routing algorithms, as modified if fault tolerant algorithms, can be utilized by irregular networks. These algorithms conventionally use several virtual channels (VCs) to pass faults and oversized nodes. In this paper, a new wormhole-switched routing algorithm for irregular 2-D mesh interconnection Network-on-Chip is proposed, where no VC is used for routing. We also improve message passing...
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