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As the technology scales toward deeper submicron, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with higher communication requirements. Network-on-chip architectures emerged as promising solutions for future system-on-chip communication architecture designs. However, the switching and routing algorithm design of network-on-chip...
This paper presents a 28Gbps voltage controlled oscillator (VCO) based clock and data recovery (CDR) with a separate proportional path technology. It employs a quarter rate ternary Bang-Bang phase detector to extract the phase error between the local clock and input data. The circuit designed in a 65nm CMOS process achieves ±1000 ppm lock-in rang, ±6000 ppm tracking range. The simulation results show...
In this paper, a low latency IFFT architecture for 3rd Generation Partnership Project (3GPP) LTE is proposed. To reduce the latency, we reorder the IFFT input data. By using the reordered input data, both the latency and the memory in stage 1 are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 42% compared with conventional architecture. The proposed...
Designers of complex SoCs have to face the issue of tuning their design to achieve low power consumption without compromising performance. A set of complementary techniques at hardware level are able to reduce power consumption but most of these techniques impact system performance and behavior. At register transfer level, low power design flows are available. Unfortunately, equivalent design flows...
A large number of computer applications(like Computer Graphics, Control Systems, Modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating...
This paper deals with design of Digital Pulse Width Modulator (DPWM) and Digital Pulse Frequency Modulator (DPWM) architectures with block RAM available in FPGA. Variable duty cycle pulse and variable frequency pulse are generated to control the switch of power converters. The proposed dual mode DPWM/DPFM architecture can control the switch of power converter under light and heavy load conditions...
The main challenge for a design engineer is not only to design a successful SoC with a well-structured and synthesizable RTL code but also to design it with efficient in energy and optimized in power consumption. The aim of the paper is to implement AMBA APB (advanced microcontroller bus architecture — advanced peripheral bus) Bridge with efficient deployment of system resources. For this, simulation...
This paper presents a phase independent 66:8 gearbox design for 100GE PCS TX system, compatible with IEEE P802.3ba standard. By using a kind of phase independent architecture, the gearbox can convert data width from 66-bit to 8-bit stably. In addition, architecture optimization and pipeline technique are also applied to increase the working speed of the gearbox circuit. The optimized PCS TX circuit...
We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
Prototyping distributed embedded system can be seen as a collection of many requirements covering many domains. System designers and developers need to describe both functional and non-functional requirements. Building distributed systems is a very tedious task since the application has to be verifiable and analyzable. Architecture Analysis and Design Language (AADL) provides adequate syntax and semantics...
In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average...
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth...
Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent...
This paper proposes a low power implementation of a non-overlapping clock (NOC) generator based on area efficient realization of Gate-Diffusion-Input (GDI) D flip-flops. The design is programmable for the number of required phases of the NOC and the amount of non-overlap period, legitimate over the wide range of frequency. The derived clocking scheme can be used for various dynamic or multi-phase...
A 5GHz Gated VCO for burst-mode operation in 10Gbps GPON and EPON systems is presented. The GVCO consists of four stages of XNOR/XOR cell with voltage-controlled delays, and aligns output clock to burst data within 2 bits time. The GVCO has a tuning range from 4.4GHz to 6.2GHz. The phase noise of the GVCO in steady state circuit is -105dBc/Hz at 5MHz offset. The circuit is implemented in SMIC 0.18μm...
Power consumption has become one of the most important differentiating factors for semiconductor products. Voltage is the strongest handle for managing chip power consumption. We look in detail at some of key power management techniques such as power gating, adaptive voltage scaling and active body-bias that leverage voltage as a handle. We discuss the implications of power management architecture...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area efficient. However, the readout power becomes large and the cycle time increases due to peripheral circuits. The 10T single-end SRAM is our proposed SRAM, in which a dedicated inverter...
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