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The inspection of the current and voltage waveforms at the current source reference planes of transistor models provides power amplifier (PA) designers with useful insights for identifying the class of operation of PAs. However when a specific class of operation at the current source reference plane is targeted, time-consuming multi-harmonic load- and source-pull simulations are required. Alternatively...
Waveform engineering is commonly used to optimize the power efficiency, linearity and output power of power amplifiers (PA). In this search for the optimal waveforms, PA designers have become interested in knowing the internal mode of operation of the device at the current-source reference-planes. However given the huge search space for the input and output multi-harmonic terminations required to...
Wideband high power generation is an essential and challenging part of many Terahehrtz systems. In this paper we review some of our recent demonstrations of Si/SiGe THz frequency multipliers that generate a wideband high power signal. The proposed design techniques blend the nonlinear modeling of the active device with new circuit topologies and high efficiency microwave structures. In the first prototype,...
This paper discusses design of in-package reactances that can optimize efficiency of power amplifier transistors by specific and well-defined harmonic terminations and pre-matching within the device package. The methodology uses a passive fundamental-only load-pull tuner to characterize the transistor. As an example, the method is applied to a 10-W Infineon LDMOS device at a fundamental frequency...
In this paper, a hybrid high-order behavioural model is proposed to mimic the response of strongly nonlinear unmatched RF transistors. In this model, a high-order Multi-Harmonic Volterra (MHV) behavioural model is used to predict the DC and fundamental frequency components of the output signal, while higher harmonic components are predicted by the Poly-Harmonic Distortion (PHD) model. The added coefficients...
Divide-by-three frequency dividers, based on a parallel injection, are analyzed and the actual locking phenomenon underlying their operation is shown. Analytical results allow us to predict the output steady-states and the locking range in terms of the circuit parameters, thus obtaining useful design insights. The derived results are shown to be very close to SPICE simulation results for a 0.13μm...
In the paper, a nonlinear method is presented which is used to analyse the phase noise of RF and microwave oscillators in the time domain. It leads to exact design rules and provides us with the design guide for the key components of the oscillator. A circuit simulation at 1GHz is presented to confirm the theoretical results. The simulation and optimization of the oscillator are carried out with Advanced...
This paper presents a method for synthesizing the package of power GaN transistors in order to achieve wideband matching at harmonics. The proposed method is applied to optimize the package of a 15W power GaN HEMT for high efficiency performance over 39% bandwidth (S-band). It is demonstrated that the internal pre-matching of package ensures that the impedance seen by the GaN die at the second-harmonic...
The suitability of the compact model HICUM for a state-of-the-art Silicon-Germanium (SiGe) heterojunction bipolar transistor (HBT) technology is evaluated with special emphasis on an efficient scalable modeling methodology. Multifinger HBTs particularly applicable to power applications are modeled. For modeling the critical self-heating effect a distributed thermal network is applied, yielding only...
This paper presents a high efficiency push-pull inverse class-F (class-F-1) power amplifier (PA) using a gallium nitride (GaN) transistor for class-S system - a digitally controlled by delta-sigma modulation. To enhance a drain efficiency of class-F-1 PA, the chip-on-board (COB) technique, which can reduce the external parasitic components of the packaged transistor and allow fast switching operation...
This paper presents a method for synthesizing the package of power GaN transistors in order to achieve wideband matching at harmonics. The proposed method is applied to optimize the package of a 15W power GaN HEMT for high efficiency performance over 39% bandwidth (S-band). It is demonstrated that the internal pre-matching of package ensures that the impedance seen by the GaN die at the second-harmonic...
Arbitrary-load-dependent X-parameters, automatically measured with a load-tuner working with an NVNA, are used to characterize and model a packaged 10W GaN transistor. A full nonlinear two-port functional block model for PA and other circuit design is immediately available for nonlinear simulation. It is demonstrated that the model predicts well the independent effects of harmonic load tuning without...
To estimate OIP3 of low power RF amplifiers from DC power operating conditions is of a good help at the beginning of the design work. We introduce a simple formula intended for estimation of OIP3 of Bipolar Junctions Transistors. Harmonic balance simulations and measurements were carried out to validate usability of this formula. The results show that there is more relation between OIP3 and the collector...
This paper reviews and contrasts two complementary device modeling approaches based on data readily obtainable from a nonlinear vector network analyzer (NVNA). The first approach extends the application of waveform data to improve the characterization, parameter extraction, and validation methodologies for “compact” transistor models. NVNA data is used to train artificial neural network -based constitutive...
In this paper a multiply by five class-E based multiplier circuit with a 32 MHz input signal is described and measurement results, performed on a prototype board, are presented and compared with a classical high frequency simulation tool. Here we don't propose a novel project methodology, but illustrate all the simulation steps and measurements results for an HF class E times five frequency multipliers...
Integrating power amplifiers (PAs) is one of the challenges for system-on-chip (SOC) applications due to the low breakdown voltage of nanoscale CMOS devices. This paper presents the study and design of three class-E PAs based on lumped element load transformation networks (LTNs) in 90nm CMOS process for LTE band, i.e. 2.55 GHz. The simulation results show that the designed PAs can deliver an output...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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