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The paper presents a 24 V chopper offset-stabilized operational amplifier with symmetrical RC notch filters, having a 4–24 V supply range, and being realized using a 0.25 ßm BCD process. The amplifier has a typical offset voltage of 1.2 μV, a minimum PSRR of 128 dB, a minimum CMRR of 120 dB, a minimum open-loop gain of 134dB, a noise PSD of 30 nV/√Hz, 1.8 MHz unity gain bandwidth, and THD + noise...
This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a...
This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (< 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and minimum number of external components required for...
In this paper a voltage differentiator based on OTA-C structure is introduced. To maintain a large time constant for biological signal processing at pico farad range filter capacitor, the input voltage attenuator is applied to reduce the overall transconductance gain of this OTA. This OTA-C voltage differentiator is simulated on a standard CMOS 0.35µm process and operated at 1.2 V with 4.8 nW power...
This paper presents a novel two-step pixel-level analog-to-digital converter (ADC) design, which is embedded in a 17μm-pitch pixel for Infrared Focal Plane Array (IRFPA). Digitization includes two successive steps: the first is reciprocal and the second linear. With the reciprocal conversion, a high dynamic range is achieved, and the linear conversion, on the other hand, guarantees a suitable frame...
This paper concerns the design and the implementation of a transimpedance amplifier (TIA) dedicated to detector of Near Infrared spectroscopy (NIRS). To reduce the effect of the input capacitance on the bandwidth, a bias circuit with low input impedance is connected to input stage. A single ended common source common gate input stage based on a cascode structure is used to get a higher gain bandwidth...
We present a 56-channel neural recording interface with a chopper-stabilized DC-coupled front-end and a programmable mixed-signal DC cancelation feedback. Each recording channel has a fully-differential amplifier with 51–54dB of gain, an input-referred noise of 5µVrms integrated from 10Hz to 5kHz and a CMRR of 65dB. Input DC-coupling allows for a simple chopping scheme without the area overhead of...
The hybrid fully differential second order Gm — C lowpass filter constructed from an operational transconductance amplifier and a PMOS source follower is presented in this paper. This proposed LPF is simulated using 0.35 μm standard CMOS process and consumes 9.19 nW at 1.5 V power supply for 100 Hz bandwidth. The bandwidth of this proposed LPF is tunable from 10 Hz to 1 kHz. The benchmarks between...
An operational amplifier is described which uses separate loops to control the output voltage and the error voltage between its inputs. To a large extent this architecture combines the high-speed characteristics of “current feedback” amplifiers with the low input referred errors of precision architectures. The technique has been applied to produce an amplifier with precision characteristics comparable...
A wideband, low-power, low-noise and area-efficient analog front-end (AFE) for acquiring neural signals is described. The AFE builds upon existing architectures but uses block-wise optimization to achieve superior performance when used in a multichannel system with scalable channel count. The AFE is also the first of its kind to enable acquisition from extended neural bandwidths greater than 10 kHz...
In this paper, a CMOS neural amplifier based on memcapacitor has been realized. A memcapacitor is a new element based on memristor. A performance comparison between memcapacitor based realization and conventional integrated one has been introduced. The circuits were simulated using 90nm CMOS technology, Vdd = 1.2v, for a total input referred noise of 1.97 µVrms and a total power consumption of 1.28...
The paths for power supply noise leakage in low drop-out (LDO) voltage regulators are analyzed, and techniques are discussed to minimize their effects on the output voltage. An internally compensated high power supply rejection (PSR) LDO voltage regulator with adaptive supply noise compensation scheme is presented. Its regulated output voltage is 1.6 V to provide 0–50 mA of current with a power supply...
This paper presents a power-supply noise canceller (PSNC) for current-steering DAC for high-speed and high-throughput wireless communication systems. Proposed PSNC effectively detects power-supply noise (PSN) and controls the current sources so that PSN would be removed at the output signal. The fabricated 2.24-GHz, 6-bit DAC has demonstrated a maximum of 8.4-dB PSN-reduction. Also, this DAC achieved...
A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10...
This paper introduces the detrimental effects of voltage regulator noise on ΔVBE-based temperature sense circuits. The work began when a significant temperature reporting inaccuracy was observed on a commercial DC-DC power conversion module. In the paper, the observed problem will be discussed, and a Spice model presented which allows the issue to be simulated. The main part of the work, however,...
In this paper, an approach towards high speed current mode based SAR ADCs is presented. The main focus is placed on the design of a unary single-sided current steering DAC working with a binary search algorithm inside the SAR loop. Reflecting the fact that current source matching and precise current settling are the most important static and dynamic properties of the current steering DAC in a current...
The paper presents the design of a fully differential gain boosted operational amplifier (opamp). The opamp is designed for high performance analog-to-digital converter (ADC). Both the main opamp and the boosted opamp are fully differential folded-cascode opamp. The main opamp has a switch capacitor common mode feedback circuit. The opamp is designed in 0.13m CMOS process with 1.2V power supply. Spectre...
Passive cancellation of common mode (cm) noise is a very promising alternative to a conventional cm filter. The basic idea has already been described in literature. However, a thorough theoretical investigation regarding the flyback that shows that perfect compensation should be possible, has not been published yet. The investigation given provides a deeper insight into passive compensation and balancing...
A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process,...
Design, implementation and measurement of low power CMOS analog baseband stages used in a Medical Implant Communication Service and Body Area Network receivers are presented. The analog stages presented in this work include an operational transconductance amplifier, a 5th order tunable active elliptic filter and a limiting amplifier. The designs are implemented in IBM 0.18 μm RF CMOS process using...
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