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Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
Data centers availability is mandatory and is conditioned by a quick response to failures and attacks thanks to efficient live forensics. However, this task is lately impossible to complete with classic systems because of encountered data rates and service diversity. Moreover, Software-Defined Networking (SDN) devices agility requirements prevent the use of Application Specific Integrated Circuits...
Pathfinding algorithms are at the heart of several classes of applications, such as network appliances (routing), GPS navigation and autonomous cars, which are related to recent trends in Artificial Intelligence and Internet of Things (IoT). Moreover, advances in semiconductor miniaturization technologies have enabled the design of efficient Systems-on-Chip (SoC) devices, with demanding performance...
Most networking performance enhancements occur through specific static solutions, where the structure of the protocol stack remains unchanged. Instead, we focus on a flexible software and hardware co-design for the entire protocol stack. In this paper, we present EmbedNet, a System-on-Chip implementation of a flexible network architecture for the Future Internet, where parts of the protocol stack...
Software Defined Networking (SDN) has been described as the hope and hype for the future of networking. Definitions vary, but one research direction has been to separate the control plane from the data plane, introducing abstractions that can provide a global network view, a description of required behavior, and a model of packet forwarding. This is intended as a way to open up the closed-box and...
The ability of ultra-low latency to process market data feed is the premise and foundation for a today's trading system to grab the instant trading profits. The market data feed containing up-to-date information on market changes is multicasted real-timely from financial exchanges to market participants, usually in the form of financial information exchange (FIX) Adapted for STreaming (FAST) protocol...
In the recent years, wireless technology has arised as a promising alternative to ethernet technology as a transmission medium for industrial automation system. This paper presents our wireless solution for industrial application, which is based on wireless LAN (WLAN) system. In this paper, our proposed system on chip (SoC) design and FPGA implementation for industrial wireless local area network...
To satisfy more and more complicated requirements on information recording, processing, exchange etc. in newly developed intelligent satellites, a distributed storage system is designed based on SpaceWire network in satellite platform. In this distributed storage system, a SpaceWire router unit serving as the core device of star network connects several nodes, including onboard computers, namely,...
Sensitive data are usually transferred within a vehicle using FlexRay protocol. To prevent the in-vehicle data from the manipulation and man-in-the-middle attacks through On Board Diagnostic (OBD-II) port, appropriate security schemes should be applied. In this paper, we propose a scheme to embed data integrity and confidentiality into the original FlexRay data frames and reuse the Cyclic Redundancy...
Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CAN's frame rate of the system. The bit's positions of the redundant...
EURECA architectures have been proposed as an enhancement to existing FPGAs, to enable cycle-by-cycle reconfiguration. Applications with irregular data accesses, which previously cannot be efficiently supported in hardware, can be efficiently mapped into EURECA architectures. One major challenge to apply the EURECA architectures to practical applications is the intensive design efforts required to...
Asynchronous paradigm is another option for the project of digital systems. Several design styles can be used, where the micropipeline style is the most suitable one for FPGA platforms because it has a simpler control. It is proposed new pipeline architecture to implement asynchronous systems, in bundled-data micropipeline style, having FPGAs as target devices. One drawback of the bundled-data design...
Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing...
Modern computer networks need components that can evolve to support both the latest bandwidth demands and new protocols and features. To address this need, we propose a new programmable packet processor architecture built from an FPGA containing an embedded Network-on-Chip (NoC). The architecture is highly flexible, providing more programmability than is possible in an ASIC-based design, while supporting...
This paper presents the Hardware/Software (HW/SW) implementation of Scalar Multiplication (SM) for Elliptic Curve Cryptosystem (ECC) over prime field Fp At low level of abstraction, the SM execution is based on the Modular Addition Subtraction (MAS) and the Modular Multiplication (MM) operations. In this work, we propose the implementation of the SM as a Programmable System on Chip (PSoC), using the...
The link between the processor and memory is one of the last remaining parallel buses and a major performance bottleneck in computer systems. The Hybrid Memory Cube (HMC) was developed with the goal of helping overcome this ’memory wall’. In contrast to DDRx memory interfaces, the HMC host interface is serial and packetized. This paper presents a vendor-agnostic, open-source implementation of an HMC...
Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. In this work, we compare parity-based error detection with software-based retry, and LTMR on a reference architecture regarding maximum frequency, area overhead and processing time. Our results show that our solution based on parity-based error-detection saves from...
It has been shown in previous works that non-uniform sampling and processing is a better scheme than the uniform sampling to sample and process low activity signals. Non-uniform sampling technique generates fewer samples, which means less data to process and lower power consumption. Furthermore, asynchronous logic is known to be data-driven. It proves to be more adapted to the non-uniform sampling...
Carrying out network monitoring tasks remains a continuous challenge, partially because the line rate reaches and exceeds 100 Gbit/s. Besides the increasing data rate, the advent of programmable networks necessitates efficient solutions for supporting packet processing tasks in an adaptive way. Introducing a modification of a protocol or any new protocol in such a flexible infrastructure implies a...
The Internet of Things (IoT) is a dynamic, ever-evolving “living” entity. Hence, modern Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities, which allow in-field non-invasive modifications to the circuit implemented on the FPGA, are an ideal fit. Usually, the activation of DPR capabilities requires the procurement of additional licenses from the FPGA...
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